
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7423438
[patent_doc_number] => 20040229414
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-18
[patent_title] => 'FET having epitaxial silicon growth'
[patent_app_type] => new
[patent_app_number] => 10/758059
[patent_app_country] => US
[patent_app_date] => 2004-01-15
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[patent_no_of_words] => 3956
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[pdf_file] => publications/A1/0229/20040229414.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/758059 | FET having epitaxial silicon growth | Jan 14, 2004 | Issued |
Array
(
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[patent_issue_date] => 2004-10-14
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/755680 | Method of manufacturing semiconductor device | Jan 12, 2004 | Abandoned |
Array
(
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[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Method of manufacturing semiconductor device having impurity region under isolation region'
[patent_app_type] => utility
[patent_app_number] => 10/748273
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[patent_app_date] => 2003-12-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/748273 | Method of manufacturing semiconductor device having impurity region under isolation region | Dec 30, 2003 | Issued |
Array
(
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[patent_kind] => B2
[patent_issue_date] => 2006-02-28
[patent_title] => 'Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 10/707444
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[patent_drawing_sheets_cnt] => 10
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Array
(
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[patent_title] => 'Method of fabricating integrated circuitry, and method of forming a conductive line'
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[patent_app_country] => US
[patent_app_date] => 2003-12-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/729260 | Method of fabricating integrated circuitry | Dec 4, 2003 | Issued |
Array
(
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[patent_title] => 'Method of maintaining photolithographic precision alignment after wafer bonding process'
[patent_app_type] => utility
[patent_app_number] => 10/722603
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Array
(
[id] => 948819
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[patent_issue_date] => 2005-11-08
[patent_title] => 'Method of forming a porous material layer in a semiconductor device'
[patent_app_type] => utility
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[patent_app_date] => 2003-10-31
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[pdf_file] => patents/06/962/06962855.pdf
[firstpage_image] =>[orig_patent_app_number] => 10697053
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/697053 | Method of forming a porous material layer in a semiconductor device | Oct 30, 2003 | Issued |
Array
(
[id] => 737328
[patent_doc_number] => 07033934
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[patent_kind] => B2
[patent_issue_date] => 2006-04-25
[patent_title] => 'Method of production of semiconductor package'
[patent_app_type] => utility
[patent_app_number] => 10/693374
[patent_app_country] => US
[patent_app_date] => 2003-10-24
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[pdf_file] => patents/07/033/07033934.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/693374 | Method of production of semiconductor package | Oct 23, 2003 | Issued |
Array
(
[id] => 1060818
[patent_doc_number] => 06853358
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[patent_kind] => B2
[patent_issue_date] => 2005-02-08
[patent_title] => 'Method and device for driving a plasma display panel'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/686573 | Method and device for driving a plasma display panel | Oct 16, 2003 | Issued |
Array
(
[id] => 7161832
[patent_doc_number] => 20050084990
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[patent_issue_date] => 2005-04-21
[patent_title] => 'Endpoint detection in manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/685484
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[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10685484
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/685484 | Endpoint detection in manufacturing semiconductor device | Oct 15, 2003 | Abandoned |
Array
(
[id] => 7605448
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[patent_issue_date] => 2006-10-03
[patent_title] => 'Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate'
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Array
(
[id] => 574493
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[patent_title] => 'Die pillar structures and a method of their formation'
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Array
(
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[patent_title] => 'Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication thereof'
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Array
(
[id] => 7221667
[patent_doc_number] => 20040072379
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[patent_title] => 'Semiconductor laser with a lattice structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/677903 | Semiconductor laser with a lattice structure | Oct 1, 2003 | Issued |
Array
(
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Array
(
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Array
(
[id] => 679713
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[patent_title] => 'Unidirectionally conductive materials for interconnection'
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Array
(
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[patent_title] => 'PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER'
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Array
(
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[patent_title] => 'Electroless copper plating of electronic device components'
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Array
(
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[patent_title] => 'Pseudomorphic high electron mobility field effect transistor with high device linearity'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/667589 | Pseudomorphic high electron mobility field effect transistor with high device linearity | Sep 22, 2003 | Issued |