Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7423438 [patent_doc_number] => 20040229414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'FET having epitaxial silicon growth' [patent_app_type] => new [patent_app_number] => 10/758059 [patent_app_country] => US [patent_app_date] => 2004-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3956 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20040229414.pdf [firstpage_image] =>[orig_patent_app_number] => 10758059 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/758059
FET having epitaxial silicon growth Jan 14, 2004 Issued
Array ( [id] => 7184200 [patent_doc_number] => 20040203214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/755680 [patent_app_country] => US [patent_app_date] => 2004-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1759 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20040203214.pdf [firstpage_image] =>[orig_patent_app_number] => 10755680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755680
Method of manufacturing semiconductor device Jan 12, 2004 Abandoned
Array ( [id] => 658093 [patent_doc_number] => 07105389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Method of manufacturing semiconductor device having impurity region under isolation region' [patent_app_type] => utility [patent_app_number] => 10/748273 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 38 [patent_no_of_words] => 13346 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/105/07105389.pdf [firstpage_image] =>[orig_patent_app_number] => 10748273 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/748273
Method of manufacturing semiconductor device having impurity region under isolation region Dec 30, 2003 Issued
Array ( [id] => 769040 [patent_doc_number] => 07005339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/707444 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3959 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/005/07005339.pdf [firstpage_image] =>[orig_patent_app_number] => 10707444 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707444
Method of integrating high voltage metal oxide semiconductor devices and submicron metal oxide semiconductor devices Dec 14, 2003 Issued
Array ( [id] => 7304974 [patent_doc_number] => 20040115914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Method of fabricating integrated circuitry, and method of forming a conductive line' [patent_app_type] => new [patent_app_number] => 10/729260 [patent_app_country] => US [patent_app_date] => 2003-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3092 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20040115914.pdf [firstpage_image] =>[orig_patent_app_number] => 10729260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/729260
Method of fabricating integrated circuitry Dec 4, 2003 Issued
Array ( [id] => 944092 [patent_doc_number] => 06967145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Method of maintaining photolithographic precision alignment after wafer bonding process' [patent_app_type] => utility [patent_app_number] => 10/722603 [patent_app_country] => US [patent_app_date] => 2003-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2174 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967145.pdf [firstpage_image] =>[orig_patent_app_number] => 10722603 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/722603
Method of maintaining photolithographic precision alignment after wafer bonding process Nov 27, 2003 Issued
Array ( [id] => 948819 [patent_doc_number] => 06962855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-08 [patent_title] => 'Method of forming a porous material layer in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/697053 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/962/06962855.pdf [firstpage_image] =>[orig_patent_app_number] => 10697053 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697053
Method of forming a porous material layer in a semiconductor device Oct 30, 2003 Issued
Array ( [id] => 737328 [patent_doc_number] => 07033934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Method of production of semiconductor package' [patent_app_type] => utility [patent_app_number] => 10/693374 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2901 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/033/07033934.pdf [firstpage_image] =>[orig_patent_app_number] => 10693374 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/693374
Method of production of semiconductor package Oct 23, 2003 Issued
Array ( [id] => 1060818 [patent_doc_number] => 06853358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Method and device for driving a plasma display panel' [patent_app_type] => utility [patent_app_number] => 10/686573 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5913 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853358.pdf [firstpage_image] =>[orig_patent_app_number] => 10686573 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686573
Method and device for driving a plasma display panel Oct 16, 2003 Issued
Array ( [id] => 7161832 [patent_doc_number] => 20050084990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Endpoint detection in manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/685484 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2427 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20050084990.pdf [firstpage_image] =>[orig_patent_app_number] => 10685484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/685484
Endpoint detection in manufacturing semiconductor device Oct 15, 2003 Abandoned
Array ( [id] => 7605448 [patent_doc_number] => 07115481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate' [patent_app_type] => utility [patent_app_number] => 10/686084 [patent_app_country] => US [patent_app_date] => 2003-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 24 [patent_no_of_words] => 4757 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/115/07115481.pdf [firstpage_image] =>[orig_patent_app_number] => 10686084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/686084
Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate Oct 13, 2003 Issued
Array ( [id] => 574493 [patent_doc_number] => 07462942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Die pillar structures and a method of their formation' [patent_app_type] => utility [patent_app_number] => 10/682054 [patent_app_country] => US [patent_app_date] => 2003-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 1746 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/462/07462942.pdf [firstpage_image] =>[orig_patent_app_number] => 10682054 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682054
Die pillar structures and a method of their formation Oct 8, 2003 Issued
Array ( [id] => 1053143 [patent_doc_number] => 06858470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-22 [patent_title] => 'Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication thereof' [patent_app_type] => utility [patent_app_number] => 10/682273 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4001 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/858/06858470.pdf [firstpage_image] =>[orig_patent_app_number] => 10682273 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/682273
Method for fabricating semiconductor packages, and leadframe assemblies for the fabrication thereof Oct 7, 2003 Issued
Array ( [id] => 7221667 [patent_doc_number] => 20040072379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Semiconductor laser with a lattice structure' [patent_app_type] => new [patent_app_number] => 10/677903 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3175 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20040072379.pdf [firstpage_image] =>[orig_patent_app_number] => 10677903 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/677903
Semiconductor laser with a lattice structure Oct 1, 2003 Issued
Array ( [id] => 944309 [patent_doc_number] => 06967363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-22 [patent_title] => 'Lateral diode with multiple spacers' [patent_app_type] => utility [patent_app_number] => 10/676904 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4416 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967363.pdf [firstpage_image] =>[orig_patent_app_number] => 10676904 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/676904
Lateral diode with multiple spacers Sep 30, 2003 Issued
Array ( [id] => 7609842 [patent_doc_number] => 06998346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Method for the patterned, selective metallization of a surface of a substrate' [patent_app_type] => utility [patent_app_number] => 10/675634 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2625 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/998/06998346.pdf [firstpage_image] =>[orig_patent_app_number] => 10675634 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/675634
Method for the patterned, selective metallization of a surface of a substrate Sep 29, 2003 Issued
Array ( [id] => 679713 [patent_doc_number] => 07084053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Unidirectionally conductive materials for interconnection' [patent_app_type] => utility [patent_app_number] => 10/676294 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4938 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084053.pdf [firstpage_image] =>[orig_patent_app_number] => 10676294 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/676294
Unidirectionally conductive materials for interconnection Sep 29, 2003 Issued
Array ( [id] => 1073714 [patent_doc_number] => 06838379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER' [patent_app_type] => utility [patent_app_number] => 10/676934 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4362 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838379.pdf [firstpage_image] =>[orig_patent_app_number] => 10676934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/676934
PROCESS FOR REDUCING IMPURITY LEVELS, STRESS, AND RESISTIVITY, AND INCREASING GRAIN SIZE OF COPPER FILLER IN TRENCHES AND VIAS OF INTEGRATED CIRCUIT STRUCTURES TO ENHANCE ELECTRICAL PERFORMANCE OF COPPER FILLER Sep 29, 2003 Issued
Array ( [id] => 7217443 [patent_doc_number] => 20040154929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Electroless copper plating of electronic device components' [patent_app_type] => new [patent_app_number] => 10/669633 [patent_app_country] => US [patent_app_date] => 2003-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2337 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20040154929.pdf [firstpage_image] =>[orig_patent_app_number] => 10669633 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/669633
Electroless copper plating of electronic device components Sep 24, 2003 Abandoned
Array ( [id] => 7404257 [patent_doc_number] => 20040262626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Pseudomorphic high electron mobility field effect transistor with high device linearity' [patent_app_type] => new [patent_app_number] => 10/667589 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3154 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20040262626.pdf [firstpage_image] =>[orig_patent_app_number] => 10667589 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/667589
Pseudomorphic high electron mobility field effect transistor with high device linearity Sep 22, 2003 Issued
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