
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1138126
[patent_doc_number] => 06780695
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-08-24
[patent_title] => 'BiCMOS integration scheme with raised extrinsic base'
[patent_app_type] => B1
[patent_app_number] => 10/249563
[patent_app_country] => US
[patent_app_date] => 2003-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 4726
[patent_no_of_claims] => 17
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[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/780/06780695.pdf
[firstpage_image] =>[orig_patent_app_number] => 10249563
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249563 | BiCMOS integration scheme with raised extrinsic base | Apr 17, 2003 | Issued |
Array
(
[id] => 6664222
[patent_doc_number] => 20030203548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-30
[patent_title] => 'Method of fabricating integrated circuitry, method of forming a local interconnect, and method of forming a conductive line.'
[patent_app_type] => new
[patent_app_number] => 10/418540
[patent_app_country] => US
[patent_app_date] => 2003-04-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0203/20030203548.pdf
[firstpage_image] =>[orig_patent_app_number] => 10418540
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/418540 | Method of forming a local interconnect | Apr 16, 2003 | Issued |
Array
(
[id] => 6802841
[patent_doc_number] => 20030230235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-18
[patent_title] => 'Dislocation reduction in non-polar gallium nitride thin films'
[patent_app_type] => new
[patent_app_number] => 10/413913
[patent_app_country] => US
[patent_app_date] => 2003-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20030230235.pdf
[firstpage_image] =>[orig_patent_app_number] => 10413913
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/413913 | Dislocation reduction in non-polar gallium nitride thin films | Apr 14, 2003 | Issued |
Array
(
[id] => 7184259
[patent_doc_number] => 20040203228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-14
[patent_title] => 'METHOD OF FORMING A TUNGSTEN PLUG'
[patent_app_type] => new
[patent_app_number] => 10/249444
[patent_app_country] => US
[patent_app_date] => 2003-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 1697
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[pdf_file] => publications/A1/0203/20040203228.pdf
[firstpage_image] =>[orig_patent_app_number] => 10249444
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249444 | METHOD OF FORMING A TUNGSTEN PLUG | Apr 9, 2003 | Abandoned |
Array
(
[id] => 1152250
[patent_doc_number] => 06767821
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-07-27
[patent_title] => 'Method for fabricating an interconnect line'
[patent_app_type] => B1
[patent_app_number] => 10/426354
[patent_app_country] => US
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/767/06767821.pdf
[firstpage_image] =>[orig_patent_app_number] => 10426354
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/426354 | Method for fabricating an interconnect line | Apr 6, 2003 | Issued |
Array
(
[id] => 6863734
[patent_doc_number] => 20030189260
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'FLIP-CHIP BONDING STRUCTURE AND METHOD THEREOF'
[patent_app_type] => new
[patent_app_number] => 10/249323
[patent_app_country] => US
[patent_app_date] => 2003-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0189/20030189260.pdf
[firstpage_image] =>[orig_patent_app_number] => 10249323
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249323 | FLIP-CHIP BONDING STRUCTURE AND METHOD THEREOF | Mar 31, 2003 | Abandoned |
Array
(
[id] => 6612217
[patent_doc_number] => 20030209805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Flourine doped SiO2 film and method of fabrication'
[patent_app_type] => new
[patent_app_number] => 10/396659
[patent_app_country] => US
[patent_app_date] => 2003-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3071
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20030209805.pdf
[firstpage_image] =>[orig_patent_app_number] => 10396659
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/396659 | Flourine doped SiO2 film and method of fabrication | Mar 23, 2003 | Abandoned |
Array
(
[id] => 749677
[patent_doc_number] => 07022579
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-04
[patent_title] => 'Method for filling via with metal'
[patent_app_type] => utility
[patent_app_number] => 10/388264
[patent_app_country] => US
[patent_app_date] => 2003-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/07/022/07022579.pdf
[firstpage_image] =>[orig_patent_app_number] => 10388264
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/388264 | Method for filling via with metal | Mar 13, 2003 | Issued |
Array
(
[id] => 7673318
[patent_doc_number] => 20040180461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Light guide for image sensor'
[patent_app_type] => new
[patent_app_number] => 10/388274
[patent_app_country] => US
[patent_app_date] => 2003-03-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0180/20040180461.pdf
[firstpage_image] =>[orig_patent_app_number] => 10388274
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/388274 | Image sensor device and method to form image sensor device | Mar 11, 2003 | Issued |
Array
(
[id] => 1107743
[patent_doc_number] => 06809016
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-26
[patent_title] => 'Diffusion stop implants to suppress as punch-through in SiGe'
[patent_app_type] => B1
[patent_app_number] => 10/379794
[patent_app_country] => US
[patent_app_date] => 2003-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/809/06809016.pdf
[firstpage_image] =>[orig_patent_app_number] => 10379794
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/379794 | Diffusion stop implants to suppress as punch-through in SiGe | Mar 5, 2003 | Issued |
Array
(
[id] => 1138187
[patent_doc_number] => 06780708
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-08-24
[patent_title] => 'METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY'
[patent_app_type] => B1
[patent_app_number] => 10/382744
[patent_app_country] => US
[patent_app_date] => 2003-03-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/780/06780708.pdf
[firstpage_image] =>[orig_patent_app_number] => 10382744
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/382744 | METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY | Mar 4, 2003 | Issued |
Array
(
[id] => 7504931
[patent_doc_number] => 08035233
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-11
[patent_title] => 'Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer'
[patent_app_type] => utility
[patent_app_number] => 10/379820
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/379820 | Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer | Mar 2, 2003 | Issued |
Array
(
[id] => 6843212
[patent_doc_number] => 20030148559
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-07
[patent_title] => 'Semiconductor device and the method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/376662
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10376662
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/376662 | Method of manufacturing a semiconductor device with a vertical drain drift layer of the alternating-conductivity-type | Feb 27, 2003 | Issued |
Array
(
[id] => 1149336
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[patent_issue_date] => 2004-08-03
[patent_title] => 'Method of forming a data-storing capacitive element made in an insulating film on a semiconductor substrate'
[patent_app_type] => B2
[patent_app_number] => 10/367737
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/367737 | Method of forming a data-storing capacitive element made in an insulating film on a semiconductor substrate | Feb 18, 2003 | Issued |
Array
(
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[patent_title] => 'Method for manufacturing semiconductor device of sub-micron or high voltage CMOS structure'
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Array
(
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[patent_issue_date] => 2004-08-12
[patent_title] => 'Method of forming a pocket implant region after formation of composite insulator spacers'
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Array
(
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[patent_title] => 'Methods and apparatus for processing semiconductor wafers with plasma processing chambers in a wafer track environment'
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Array
(
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Array
(
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[patent_title] => 'Method of making an integrated photodetector in which a silicon nitride layer forms an anti-reflective film and part of multi-layer insulator within transistor structures'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/357958 | Method of making an integrated photodetector in which a silicon nitride layer forms an anti-reflective film and part of multi-layer insulator within transistor structures | Feb 3, 2003 | Issued |
Array
(
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[patent_issue_date] => 2006-04-11
[patent_title] => 'Method of producing organic semiconductor device including step of applying oxidizing agent solution to monomer layer to obtain polymer layer'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 10479364
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/479364 | Method of producing organic semiconductor device including step of applying oxidizing agent solution to monomer layer to obtain polymer layer | Feb 3, 2003 | Issued |