Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1138126 [patent_doc_number] => 06780695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'BiCMOS integration scheme with raised extrinsic base' [patent_app_type] => B1 [patent_app_number] => 10/249563 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 4726 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780695.pdf [firstpage_image] =>[orig_patent_app_number] => 10249563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249563
BiCMOS integration scheme with raised extrinsic base Apr 17, 2003 Issued
Array ( [id] => 6664222 [patent_doc_number] => 20030203548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Method of fabricating integrated circuitry, method of forming a local interconnect, and method of forming a conductive line.' [patent_app_type] => new [patent_app_number] => 10/418540 [patent_app_country] => US [patent_app_date] => 2003-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3092 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203548.pdf [firstpage_image] =>[orig_patent_app_number] => 10418540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/418540
Method of forming a local interconnect Apr 16, 2003 Issued
Array ( [id] => 6802841 [patent_doc_number] => 20030230235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Dislocation reduction in non-polar gallium nitride thin films' [patent_app_type] => new [patent_app_number] => 10/413913 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4444 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20030230235.pdf [firstpage_image] =>[orig_patent_app_number] => 10413913 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/413913
Dislocation reduction in non-polar gallium nitride thin films Apr 14, 2003 Issued
Array ( [id] => 7184259 [patent_doc_number] => 20040203228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'METHOD OF FORMING A TUNGSTEN PLUG' [patent_app_type] => new [patent_app_number] => 10/249444 [patent_app_country] => US [patent_app_date] => 2003-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1697 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20040203228.pdf [firstpage_image] =>[orig_patent_app_number] => 10249444 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249444
METHOD OF FORMING A TUNGSTEN PLUG Apr 9, 2003 Abandoned
Array ( [id] => 1152250 [patent_doc_number] => 06767821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Method for fabricating an interconnect line' [patent_app_type] => B1 [patent_app_number] => 10/426354 [patent_app_country] => US [patent_app_date] => 2003-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3710 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/767/06767821.pdf [firstpage_image] =>[orig_patent_app_number] => 10426354 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426354
Method for fabricating an interconnect line Apr 6, 2003 Issued
Array ( [id] => 6863734 [patent_doc_number] => 20030189260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'FLIP-CHIP BONDING STRUCTURE AND METHOD THEREOF' [patent_app_type] => new [patent_app_number] => 10/249323 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3110 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20030189260.pdf [firstpage_image] =>[orig_patent_app_number] => 10249323 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249323
FLIP-CHIP BONDING STRUCTURE AND METHOD THEREOF Mar 31, 2003 Abandoned
Array ( [id] => 6612217 [patent_doc_number] => 20030209805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Flourine doped SiO2 film and method of fabrication' [patent_app_type] => new [patent_app_number] => 10/396659 [patent_app_country] => US [patent_app_date] => 2003-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3071 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20030209805.pdf [firstpage_image] =>[orig_patent_app_number] => 10396659 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/396659
Flourine doped SiO2 film and method of fabrication Mar 23, 2003 Abandoned
Array ( [id] => 749677 [patent_doc_number] => 07022579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Method for filling via with metal' [patent_app_type] => utility [patent_app_number] => 10/388264 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1967 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/022/07022579.pdf [firstpage_image] =>[orig_patent_app_number] => 10388264 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388264
Method for filling via with metal Mar 13, 2003 Issued
Array ( [id] => 7673318 [patent_doc_number] => 20040180461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Light guide for image sensor' [patent_app_type] => new [patent_app_number] => 10/388274 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2971 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20040180461.pdf [firstpage_image] =>[orig_patent_app_number] => 10388274 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388274
Image sensor device and method to form image sensor device Mar 11, 2003 Issued
Array ( [id] => 1107743 [patent_doc_number] => 06809016 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Diffusion stop implants to suppress as punch-through in SiGe' [patent_app_type] => B1 [patent_app_number] => 10/379794 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2091 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/809/06809016.pdf [firstpage_image] =>[orig_patent_app_number] => 10379794 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379794
Diffusion stop implants to suppress as punch-through in SiGe Mar 5, 2003 Issued
Array ( [id] => 1138187 [patent_doc_number] => 06780708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY' [patent_app_type] => B1 [patent_app_number] => 10/382744 [patent_app_country] => US [patent_app_date] => 2003-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 9148 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780708.pdf [firstpage_image] =>[orig_patent_app_number] => 10382744 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/382744
METHOD OF FORMING CORE AND PERIPHERY GATES INCLUDING TWO CRITICAL MASKING STEPS TO FORM A HARD MASK IN A CORE REGION THAT INCLUDES A CRITICAL DIMENSION LESS THAN ACHIEVABLE AT A RESOLUTION LIMIT OF LITHOGRAPHY Mar 4, 2003 Issued
Array ( [id] => 7504931 [patent_doc_number] => 08035233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer' [patent_app_type] => utility [patent_app_number] => 10/379820 [patent_app_country] => US [patent_app_date] => 2003-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7310 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/035/08035233.pdf [firstpage_image] =>[orig_patent_app_number] => 10379820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379820
Adjacent substantially flexible substrates having integrated circuits that are bonded together by non-polymeric layer Mar 2, 2003 Issued
Array ( [id] => 6843212 [patent_doc_number] => 20030148559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Semiconductor device and the method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/376662 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10484 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20030148559.pdf [firstpage_image] =>[orig_patent_app_number] => 10376662 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/376662
Method of manufacturing a semiconductor device with a vertical drain drift layer of the alternating-conductivity-type Feb 27, 2003 Issued
Array ( [id] => 1149336 [patent_doc_number] => 06770528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method of forming a data-storing capacitive element made in an insulating film on a semiconductor substrate' [patent_app_type] => B2 [patent_app_number] => 10/367737 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 58 [patent_no_of_words] => 15027 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/770/06770528.pdf [firstpage_image] =>[orig_patent_app_number] => 10367737 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/367737
Method of forming a data-storing capacitive element made in an insulating film on a semiconductor substrate Feb 18, 2003 Issued
Array ( [id] => 6683404 [patent_doc_number] => 20030119268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method for manufacturing semiconductor device of sub-micron or high voltage CMOS structure' [patent_app_type] => new [patent_app_number] => 10/364480 [patent_app_country] => US [patent_app_date] => 2003-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119268.pdf [firstpage_image] =>[orig_patent_app_number] => 10364480 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364480
Method for manufacturing semiconductor device of sub-micron or high voltage CMOS structure Feb 11, 2003 Issued
Array ( [id] => 7235222 [patent_doc_number] => 20040157397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Method of forming a pocket implant region after formation of composite insulator spacers' [patent_app_type] => new [patent_app_number] => 10/361934 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2853 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20040157397.pdf [firstpage_image] =>[orig_patent_app_number] => 10361934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/361934
Method of forming a pocket implant region after formation of composite insulator spacers Feb 9, 2003 Issued
Array ( [id] => 7235459 [patent_doc_number] => 20040157430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Methods and apparatus for processing semiconductor wafers with plasma processing chambers in a wafer track environment' [patent_app_type] => new [patent_app_number] => 10/359853 [patent_app_country] => US [patent_app_date] => 2003-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6931 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20040157430.pdf [firstpage_image] =>[orig_patent_app_number] => 10359853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/359853
Methods and apparatus for processing semiconductor wafers with plasma processing chambers in a wafer track environment Feb 6, 2003 Abandoned
Array ( [id] => 7395158 [patent_doc_number] => 20040038495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Method of providing a thick thermal oxide in trench isolation' [patent_app_type] => new [patent_app_number] => 10/359994 [patent_app_country] => US [patent_app_date] => 2003-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3845 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038495.pdf [firstpage_image] =>[orig_patent_app_number] => 10359994 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/359994
Method of providing a thick thermal oxide in trench isolation Feb 5, 2003 Abandoned
Array ( [id] => 1112833 [patent_doc_number] => 06803249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method of making an integrated photodetector in which a silicon nitride layer forms an anti-reflective film and part of multi-layer insulator within transistor structures' [patent_app_type] => B2 [patent_app_number] => 10/357958 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2128 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803249.pdf [firstpage_image] =>[orig_patent_app_number] => 10357958 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/357958
Method of making an integrated photodetector in which a silicon nitride layer forms an anti-reflective film and part of multi-layer insulator within transistor structures Feb 3, 2003 Issued
Array ( [id] => 744755 [patent_doc_number] => 07026231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Method of producing organic semiconductor device including step of applying oxidizing agent solution to monomer layer to obtain polymer layer' [patent_app_type] => utility [patent_app_number] => 10/479364 [patent_app_country] => US [patent_app_date] => 2003-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5244 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026231.pdf [firstpage_image] =>[orig_patent_app_number] => 10479364 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/479364
Method of producing organic semiconductor device including step of applying oxidizing agent solution to monomer layer to obtain polymer layer Feb 3, 2003 Issued
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