Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6794741 [patent_doc_number] => 20030173614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Semiconductor integrated circuit device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/352133 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10594 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20030173614.pdf [firstpage_image] =>[orig_patent_app_number] => 10352133 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/352133
Semiconductor integrated circuit device and manufacturing method thereof Jan 27, 2003 Abandoned
Array ( [id] => 6676915 [patent_doc_number] => 20030227055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Semiconductor device having\\ gate with negative slope and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/341563 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3292 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227055.pdf [firstpage_image] =>[orig_patent_app_number] => 10341563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341563
Semiconductor device having gate with negative slope and method for manufacturing the same Jan 12, 2003 Issued
Array ( [id] => 7625529 [patent_doc_number] => 06723640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Method for forming contact plug of semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/331984 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 0 [patent_no_of_words] => 4546 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/723/06723640.pdf [firstpage_image] =>[orig_patent_app_number] => 10331984 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331984
Method for forming contact plug of semiconductor device Dec 30, 2002 Issued
Array ( [id] => 1223743 [patent_doc_number] => 06699769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method for fabricating capacitor using electrochemical deposition and wet etching' [patent_app_type] => B2 [patent_app_number] => 10/330353 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5065 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/699/06699769.pdf [firstpage_image] =>[orig_patent_app_number] => 10330353 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330353
Method for fabricating capacitor using electrochemical deposition and wet etching Dec 29, 2002 Issued
Array ( [id] => 7178880 [patent_doc_number] => 20050124154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method of forming copper interconnections for semiconductor integrated circuits on a substrate' [patent_app_type] => utility [patent_app_number] => 10/500494 [patent_app_country] => US [patent_app_date] => 2002-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20050124154.pdf [firstpage_image] =>[orig_patent_app_number] => 10500494 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/500494
Method of forming copper interconnections for semiconductor integrated circuits on a substrate Dec 27, 2002 Abandoned
Array ( [id] => 6847143 [patent_doc_number] => 20030166310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Method of reinforcing a mechanical microstructure' [patent_app_type] => new [patent_app_number] => 10/330644 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2474 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20030166310.pdf [firstpage_image] =>[orig_patent_app_number] => 10330644 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330644
Method of reinforcing a mechanical microstructure Dec 26, 2002 Issued
Array ( [id] => 6636514 [patent_doc_number] => 20030211730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'METHOD FOR FORMING CONTACT HOLE IN SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 10/330913 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4292 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211730.pdf [firstpage_image] =>[orig_patent_app_number] => 10330913 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330913
Method for forming contact hole in semiconductor device Dec 26, 2002 Issued
Array ( [id] => 972112 [patent_doc_number] => 06936497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Method of forming electronic dies wherein each die has a layer of solid diamond' [patent_app_type] => utility [patent_app_number] => 10/327844 [patent_app_country] => US [patent_app_date] => 2002-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 37 [patent_no_of_words] => 4943 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/936/06936497.pdf [firstpage_image] =>[orig_patent_app_number] => 10327844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327844
Method of forming electronic dies wherein each die has a layer of solid diamond Dec 23, 2002 Issued
Array ( [id] => 1062785 [patent_doc_number] => 06849529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Deep-trench capacitor with hemispherical grain silicon surface and method for making the same' [patent_app_type] => utility [patent_app_number] => 10/327043 [patent_app_country] => US [patent_app_date] => 2002-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 20 [patent_no_of_words] => 3492 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849529.pdf [firstpage_image] =>[orig_patent_app_number] => 10327043 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327043
Deep-trench capacitor with hemispherical grain silicon surface and method for making the same Dec 23, 2002 Issued
Array ( [id] => 938388 [patent_doc_number] => 06972217 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Low k polymer E-beam printable mechanical support' [patent_app_type] => utility [patent_app_number] => 10/328614 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 5144 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972217.pdf [firstpage_image] =>[orig_patent_app_number] => 10328614 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328614
Low k polymer E-beam printable mechanical support Dec 22, 2002 Issued
Array ( [id] => 6809214 [patent_doc_number] => 20030199153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Method of producing SI-GE base semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/325840 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9523 [patent_no_of_claims] => 132 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20030199153.pdf [firstpage_image] =>[orig_patent_app_number] => 10325840 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/325840
Method of producing SI-GE base semiconductor devices Dec 22, 2002 Abandoned
Array ( [id] => 6694885 [patent_doc_number] => 20030107079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/322492 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 15372 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20030107079.pdf [firstpage_image] =>[orig_patent_app_number] => 10322492 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/322492
Method for producing FET with source/drain region occupies a reduced area Dec 18, 2002 Issued
Array ( [id] => 1116948 [patent_doc_number] => 06800917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Bladed silicon-on-insulator semiconductor devices and method of making' [patent_app_type] => B2 [patent_app_number] => 10/321423 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3447 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800917.pdf [firstpage_image] =>[orig_patent_app_number] => 10321423 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/321423
Bladed silicon-on-insulator semiconductor devices and method of making Dec 16, 2002 Issued
Array ( [id] => 1252124 [patent_doc_number] => 06669738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Low profile semiconductor package' [patent_app_type] => B2 [patent_app_number] => 10/322119 [patent_app_country] => US [patent_app_date] => 2002-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2902 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/669/06669738.pdf [firstpage_image] =>[orig_patent_app_number] => 10322119 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/322119
Low profile semiconductor package Dec 15, 2002 Issued
Array ( [id] => 7304944 [patent_doc_number] => 20040115905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Method for treating substrates for microelectronics and substrates obtained by said method' [patent_app_type] => new [patent_app_number] => 10/318304 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7161 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20040115905.pdf [firstpage_image] =>[orig_patent_app_number] => 10318304 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318304
Method for treating substrates for microelectronics and substrates obtained by said method Dec 12, 2002 Issued
Array ( [id] => 948837 [patent_doc_number] => 06962873 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Nitridation of electrolessly deposited cobalt' [patent_app_type] => utility [patent_app_number] => 10/317373 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4295 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/962/06962873.pdf [firstpage_image] =>[orig_patent_app_number] => 10317373 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/317373
Nitridation of electrolessly deposited cobalt Dec 9, 2002 Issued
Array ( [id] => 1155492 [patent_doc_number] => 06764893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Method for reducing a parasitic capacitance of a semiconductive memory cell using metal mask for sidewall formation' [patent_app_type] => B2 [patent_app_number] => 10/314214 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4664 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764893.pdf [firstpage_image] =>[orig_patent_app_number] => 10314214 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314214
Method for reducing a parasitic capacitance of a semiconductive memory cell using metal mask for sidewall formation Dec 8, 2002 Issued
Array ( [id] => 813694 [patent_doc_number] => 07413966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Method of fabricating polysilicon thin film transistor with catalyst' [patent_app_type] => utility [patent_app_number] => 10/310964 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 6797 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/413/07413966.pdf [firstpage_image] =>[orig_patent_app_number] => 10310964 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310964
Method of fabricating polysilicon thin film transistor with catalyst Dec 5, 2002 Issued
Array ( [id] => 7289755 [patent_doc_number] => 20040110351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-10 [patent_title] => 'Method and structure for reduction of junction capacitance in a semiconductor device and formation of a uniformly lowered threshold voltage device' [patent_app_type] => new [patent_app_number] => 10/314023 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3315 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20040110351.pdf [firstpage_image] =>[orig_patent_app_number] => 10314023 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314023
Method and structure for reduction of junction capacitance in a semiconductor device and formation of a uniformly lowered threshold voltage device Dec 4, 2002 Abandoned
Array ( [id] => 1315635 [patent_doc_number] => 06607990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-19 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => B2 [patent_app_number] => 10/305153 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2893 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/607/06607990.pdf [firstpage_image] =>[orig_patent_app_number] => 10305153 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/305153
Semiconductor device and its manufacturing method Nov 26, 2002 Issued
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