
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6794741
[patent_doc_number] => 20030173614
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-18
[patent_title] => 'Semiconductor integrated circuit device and manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 10/352133
[patent_app_country] => US
[patent_app_date] => 2003-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 10594
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20030173614.pdf
[firstpage_image] =>[orig_patent_app_number] => 10352133
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/352133 | Semiconductor integrated circuit device and manufacturing method thereof | Jan 27, 2003 | Abandoned |
Array
(
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[patent_doc_number] => 20030227055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-11
[patent_title] => 'Semiconductor device having\\ gate with negative slope and method for manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/341563
[patent_app_country] => US
[patent_app_date] => 2003-01-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/341563 | Semiconductor device having gate with negative slope and method for manufacturing the same | Jan 12, 2003 | Issued |
Array
(
[id] => 7625529
[patent_doc_number] => 06723640
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-20
[patent_title] => 'Method for forming contact plug of semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/331984
[patent_app_country] => US
[patent_app_date] => 2002-12-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/331984 | Method for forming contact plug of semiconductor device | Dec 30, 2002 | Issued |
Array
(
[id] => 1223743
[patent_doc_number] => 06699769
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-02
[patent_title] => 'Method for fabricating capacitor using electrochemical deposition and wet etching'
[patent_app_type] => B2
[patent_app_number] => 10/330353
[patent_app_country] => US
[patent_app_date] => 2002-12-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/330353 | Method for fabricating capacitor using electrochemical deposition and wet etching | Dec 29, 2002 | Issued |
Array
(
[id] => 7178880
[patent_doc_number] => 20050124154
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Method of forming copper interconnections for semiconductor integrated circuits on a substrate'
[patent_app_type] => utility
[patent_app_number] => 10/500494
[patent_app_country] => US
[patent_app_date] => 2002-12-28
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[firstpage_image] =>[orig_patent_app_number] => 10500494
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/500494 | Method of forming copper interconnections for semiconductor integrated circuits on a substrate | Dec 27, 2002 | Abandoned |
Array
(
[id] => 6847143
[patent_doc_number] => 20030166310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-04
[patent_title] => 'Method of reinforcing a mechanical microstructure'
[patent_app_type] => new
[patent_app_number] => 10/330644
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10330644
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/330644 | Method of reinforcing a mechanical microstructure | Dec 26, 2002 | Issued |
Array
(
[id] => 6636514
[patent_doc_number] => 20030211730
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[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'METHOD FOR FORMING CONTACT HOLE IN SEMICONDUCTOR DEVICE'
[patent_app_type] => new
[patent_app_number] => 10/330913
[patent_app_country] => US
[patent_app_date] => 2002-12-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0211/20030211730.pdf
[firstpage_image] =>[orig_patent_app_number] => 10330913
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/330913 | Method for forming contact hole in semiconductor device | Dec 26, 2002 | Issued |
Array
(
[id] => 972112
[patent_doc_number] => 06936497
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-30
[patent_title] => 'Method of forming electronic dies wherein each die has a layer of solid diamond'
[patent_app_type] => utility
[patent_app_number] => 10/327844
[patent_app_country] => US
[patent_app_date] => 2002-12-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/936/06936497.pdf
[firstpage_image] =>[orig_patent_app_number] => 10327844
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/327844 | Method of forming electronic dies wherein each die has a layer of solid diamond | Dec 23, 2002 | Issued |
Array
(
[id] => 1062785
[patent_doc_number] => 06849529
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-01
[patent_title] => 'Deep-trench capacitor with hemispherical grain silicon surface and method for making the same'
[patent_app_type] => utility
[patent_app_number] => 10/327043
[patent_app_country] => US
[patent_app_date] => 2002-12-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/327043 | Deep-trench capacitor with hemispherical grain silicon surface and method for making the same | Dec 23, 2002 | Issued |
Array
(
[id] => 938388
[patent_doc_number] => 06972217
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-06
[patent_title] => 'Low k polymer E-beam printable mechanical support'
[patent_app_type] => utility
[patent_app_number] => 10/328614
[patent_app_country] => US
[patent_app_date] => 2002-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[firstpage_image] =>[orig_patent_app_number] => 10328614
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/328614 | Low k polymer E-beam printable mechanical support | Dec 22, 2002 | Issued |
Array
(
[id] => 6809214
[patent_doc_number] => 20030199153
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[patent_issue_date] => 2003-10-23
[patent_title] => 'Method of producing SI-GE base semiconductor devices'
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[patent_app_number] => 10/325840
[patent_app_country] => US
[patent_app_date] => 2002-12-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/325840 | Method of producing SI-GE base semiconductor devices | Dec 22, 2002 | Abandoned |
Array
(
[id] => 6694885
[patent_doc_number] => 20030107079
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-12
[patent_title] => 'Semiconductor device'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/322492 | Method for producing FET with source/drain region occupies a reduced area | Dec 18, 2002 | Issued |
Array
(
[id] => 1116948
[patent_doc_number] => 06800917
[patent_country] => US
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[patent_issue_date] => 2004-10-05
[patent_title] => 'Bladed silicon-on-insulator semiconductor devices and method of making'
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Array
(
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[patent_title] => 'Low profile semiconductor package'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/322119 | Low profile semiconductor package | Dec 15, 2002 | Issued |
Array
(
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Array
(
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[patent_title] => 'Nitridation of electrolessly deposited cobalt'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/317373 | Nitridation of electrolessly deposited cobalt | Dec 9, 2002 | Issued |
Array
(
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[patent_title] => 'Method for reducing a parasitic capacitance of a semiconductive memory cell using metal mask for sidewall formation'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/310964 | Method of fabricating polysilicon thin film transistor with catalyst | Dec 5, 2002 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/305153 | Semiconductor device and its manufacturing method | Nov 26, 2002 | Issued |