
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 645284
[patent_doc_number] => 07119006
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[patent_kind] => B2
[patent_issue_date] => 2006-10-10
[patent_title] => 'Via formation for damascene metal conductors in an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 10/304943
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[pdf_file] => patents/07/119/07119006.pdf
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Array
(
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[patent_issue_date] => 2004-01-27
[patent_title] => 'Method of forming the resin sealed semiconductor device using the lead frame'
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Array
(
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[patent_issue_date] => 2003-05-22
[patent_title] => 'Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers'
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Array
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[patent_title] => 'Method for forming a ternary diffusion barrier layer'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300253 | Forming a cap above a metal layer | Nov 19, 2002 | Issued |
Array
(
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[patent_title] => 'Method of forming poly tip of floating gate in split-gate memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/292624 | Method of forming poly tip of floating gate in split-gate memory | Nov 12, 2002 | Issued |
Array
(
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[patent_title] => 'Self-aligned silicide (salicide) process for strained silicon MOSFET on SiGe and structure formed thereby'
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Array
(
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[patent_title] => 'Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same'
[patent_app_type] => new
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Array
(
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[patent_title] => 'Semiconductor device having an improved local interconnect structure and a method for forming such a device'
[patent_app_type] => B2
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/285004 | Semiconductor device having an improved local interconnect structure and a method for forming such a device | Oct 30, 2002 | Issued |
Array
(
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[patent_issue_date] => 2004-06-22
[patent_title] => 'Method(s) facilitating formation of memory cell(s) and patterned conductive'
[patent_app_type] => B1
[patent_app_number] => 10/285183
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Array
(
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[patent_title] => 'Methods for producing thin layers, such as for use in integrated circuits'
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Array
(
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Array
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Array
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Array
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Array
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Array
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