Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 645284 [patent_doc_number] => 07119006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Via formation for damascene metal conductors in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/304943 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 27 [patent_no_of_words] => 6691 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119006.pdf [firstpage_image] =>[orig_patent_app_number] => 10304943 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/304943
Via formation for damascene metal conductors in an integrated circuit Nov 25, 2002 Issued
Array ( [id] => 1241129 [patent_doc_number] => 06682952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-27 [patent_title] => 'Method of forming the resin sealed semiconductor device using the lead frame' [patent_app_type] => B2 [patent_app_number] => 10/300782 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 2756 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/682/06682952.pdf [firstpage_image] =>[orig_patent_app_number] => 10300782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300782
Method of forming the resin sealed semiconductor device using the lead frame Nov 20, 2002 Issued
Array ( [id] => 6801323 [patent_doc_number] => 20030096488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers' [patent_app_type] => new [patent_app_number] => 10/301393 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2976 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096488.pdf [firstpage_image] =>[orig_patent_app_number] => 10301393 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301393
Method and semiconductor wafer configuration for producing an alignment mark for semiconductor wafers Nov 20, 2002 Issued
Array ( [id] => 7466929 [patent_doc_number] => 20040102033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Method for forming a ternary diffusion barrier layer' [patent_app_type] => new [patent_app_number] => 10/301254 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4320 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20040102033.pdf [firstpage_image] =>[orig_patent_app_number] => 10301254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301254
Method for forming a ternary diffusion barrier layer Nov 20, 2002 Abandoned
Array ( [id] => 7459558 [patent_doc_number] => 20040094836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Forming a cap above a metal layer' [patent_app_type] => new [patent_app_number] => 10/300253 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2973 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20040094836.pdf [firstpage_image] =>[orig_patent_app_number] => 10300253 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300253
Forming a cap above a metal layer Nov 19, 2002 Issued
Array ( [id] => 1270102 [patent_doc_number] => 06653188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method of forming poly tip of floating gate in split-gate memory' [patent_app_type] => B1 [patent_app_number] => 10/292624 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1776 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653188.pdf [firstpage_image] =>[orig_patent_app_number] => 10292624 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292624
Method of forming poly tip of floating gate in split-gate memory Nov 12, 2002 Issued
Array ( [id] => 6817925 [patent_doc_number] => 20030068883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Self-aligned silicide (salicide) process for strained silicon MOSFET on SiGe and structure formed thereby' [patent_app_type] => new [patent_app_number] => 10/287476 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3758 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20030068883.pdf [firstpage_image] =>[orig_patent_app_number] => 10287476 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287476
Self-aligned silicide (salicide) process for strained silicon MOSFET on SiGe and structure formed thereby Nov 4, 2002 Abandoned
Array ( [id] => 6627559 [patent_doc_number] => 20030102522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same' [patent_app_type] => new [patent_app_number] => 10/285883 [patent_app_country] => US [patent_app_date] => 2002-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4697 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20030102522.pdf [firstpage_image] =>[orig_patent_app_number] => 10285883 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/285883
Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same Oct 31, 2002 Issued
Array ( [id] => 7634793 [patent_doc_number] => 06656825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Semiconductor device having an improved local interconnect structure and a method for forming such a device' [patent_app_type] => B2 [patent_app_number] => 10/285004 [patent_app_country] => US [patent_app_date] => 2002-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4886 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656825.pdf [firstpage_image] =>[orig_patent_app_number] => 10285004 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/285004
Semiconductor device having an improved local interconnect structure and a method for forming such a device Oct 30, 2002 Issued
Array ( [id] => 1168827 [patent_doc_number] => 06753247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method(s) facilitating formation of memory cell(s) and patterned conductive' [patent_app_type] => B1 [patent_app_number] => 10/285183 [patent_app_country] => US [patent_app_date] => 2002-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 0 [patent_no_of_words] => 10596 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753247.pdf [firstpage_image] =>[orig_patent_app_number] => 10285183 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/285183
Method(s) facilitating formation of memory cell(s) and patterned conductive Oct 30, 2002 Issued
Array ( [id] => 7203703 [patent_doc_number] => 20040087080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Methods for producing thin layers, such as for use in integrated circuits' [patent_app_type] => new [patent_app_number] => 10/279743 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1386 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20040087080.pdf [firstpage_image] =>[orig_patent_app_number] => 10279743 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279743
Methods for producing thin layers, such as for use in integrated circuits Oct 22, 2002 Abandoned
Array ( [id] => 7204241 [patent_doc_number] => 20040087162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Metal sacrificial layer' [patent_app_type] => new [patent_app_number] => 10/273283 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4954 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20040087162.pdf [firstpage_image] =>[orig_patent_app_number] => 10273283 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273283
Metal sacrificial layer Oct 16, 2002 Abandoned
Array ( [id] => 1291081 [patent_doc_number] => 06630383 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer' [patent_app_type] => B1 [patent_app_number] => 10/274063 [patent_app_country] => US [patent_app_date] => 2002-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3168 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630383.pdf [firstpage_image] =>[orig_patent_app_number] => 10274063 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/274063
Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer Oct 16, 2002 Issued
Array ( [id] => 1291049 [patent_doc_number] => 06630380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM)' [patent_app_type] => B1 [patent_app_number] => 10/261303 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2862 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630380.pdf [firstpage_image] =>[orig_patent_app_number] => 10261303 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261303
Method for making three-dimensional metal-insulator-metal capacitors for dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM) Sep 29, 2002 Issued
Array ( [id] => 7278854 [patent_doc_number] => 20040061231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Interconnect structure for an integrated circuit and method of fabrication' [patent_app_type] => new [patent_app_number] => 10/261543 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2952 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061231.pdf [firstpage_image] =>[orig_patent_app_number] => 10261543 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/261543
Interconnect structure for an integrated circuit and method of fabrication Sep 29, 2002 Issued
Array ( [id] => 7394741 [patent_doc_number] => 20040038436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/247523 [patent_app_country] => US [patent_app_date] => 2002-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7092 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038436.pdf [firstpage_image] =>[orig_patent_app_number] => 10247523 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247523
Method of manufacturing a semiconductor integrated circuit device Sep 19, 2002 Abandoned
Array ( [id] => 7629390 [patent_doc_number] => 06818966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method and structure for controlling surface properties of dielectric layers in a thin film component for improved trimming' [patent_app_type] => B2 [patent_app_number] => 10/251263 [patent_app_country] => US [patent_app_date] => 2002-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5708 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818966.pdf [firstpage_image] =>[orig_patent_app_number] => 10251263 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/251263
Method and structure for controlling surface properties of dielectric layers in a thin film component for improved trimming Sep 19, 2002 Issued
Array ( [id] => 6781070 [patent_doc_number] => 20030062517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Semiconductor device with current confinement structure' [patent_app_type] => new [patent_app_number] => 10/246563 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3802 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20030062517.pdf [firstpage_image] =>[orig_patent_app_number] => 10246563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246563
Semiconductor device with current confinement structure Sep 17, 2002 Abandoned
Array ( [id] => 1031060 [patent_doc_number] => 06878612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Self-aligned contact process for semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/243684 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6900 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878612.pdf [firstpage_image] =>[orig_patent_app_number] => 10243684 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/243684
Self-aligned contact process for semiconductor device Sep 15, 2002 Issued
Array ( [id] => 6772464 [patent_doc_number] => 20030015802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Semiconductor device and a method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/242623 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20030015802.pdf [firstpage_image] =>[orig_patent_app_number] => 10242623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242623
Semiconductor device and a method of manufacturing the same Sep 12, 2002 Issued
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