Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1119753 [patent_doc_number] => 06797588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method for manufacturing a semiconductor device having a trench and a thick insulation film at the trench opening' [patent_app_type] => B2 [patent_app_number] => 10/108443 [patent_app_country] => US [patent_app_date] => 2002-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 37 [patent_no_of_words] => 3978 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797588.pdf [firstpage_image] =>[orig_patent_app_number] => 10108443 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/108443
Method for manufacturing a semiconductor device having a trench and a thick insulation film at the trench opening Mar 28, 2002 Issued
Array ( [id] => 1172912 [patent_doc_number] => 06750155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Methods to minimize moisture condensation over a substrate in a rapid cycle chamber' [patent_app_type] => B2 [patent_app_number] => 10/113014 [patent_app_country] => US [patent_app_date] => 2002-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6449 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750155.pdf [firstpage_image] =>[orig_patent_app_number] => 10113014 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/113014
Methods to minimize moisture condensation over a substrate in a rapid cycle chamber Mar 27, 2002 Issued
Array ( [id] => 7465019 [patent_doc_number] => 20040101769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Method for adjusting the overlay of two mask planes in a photolithographic process for the production of an integrated circuit' [patent_app_type] => new [patent_app_number] => 10/473434 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2614 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20040101769.pdf [firstpage_image] =>[orig_patent_app_number] => 10473434 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/473434
Method for adjusting the overlay of two mask planes in a photolithographic process for the production of an integrated circuit Mar 11, 2002 Issued
Array ( [id] => 1285221 [patent_doc_number] => 06638842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-28 [patent_title] => 'Methods of fabricating integrated circuitry' [patent_app_type] => B2 [patent_app_number] => 10/087147 [patent_app_country] => US [patent_app_date] => 2002-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3159 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/638/06638842.pdf [firstpage_image] =>[orig_patent_app_number] => 10087147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/087147
Methods of fabricating integrated circuitry Feb 27, 2002 Issued
Array ( [id] => 6706421 [patent_doc_number] => 20030153155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Fet having epitaxial silicon growth' [patent_app_type] => new [patent_app_number] => 10/073723 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4172 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 26 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20030153155.pdf [firstpage_image] =>[orig_patent_app_number] => 10073723 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/073723
FET having epitaxial silicon growth Feb 10, 2002 Issued
Array ( [id] => 5936142 [patent_doc_number] => 20020061618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Method of producing a Si-Ge base heterojunction bipolar device' [patent_app_type] => new [patent_app_number] => 09/988938 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4994 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20020061618.pdf [firstpage_image] =>[orig_patent_app_number] => 09988938 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/988938
Si-Ge base heterojunction bipolar device Jan 31, 2002 Issued
Array ( [id] => 5828669 [patent_doc_number] => 20020068380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/058716 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 20534 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20020068380.pdf [firstpage_image] =>[orig_patent_app_number] => 10058716 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/058716
Method of manufacturing a ball grid array type semiconductor package Jan 29, 2002 Issued
Array ( [id] => 7235235 [patent_doc_number] => 20050079693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask' [patent_app_type] => utility [patent_app_number] => 10/495673 [patent_app_country] => US [patent_app_date] => 2002-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3120 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20050079693.pdf [firstpage_image] =>[orig_patent_app_number] => 10495673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/495673
Mask for crystallizing polysilicon and a method for forming thin film transistor using the mask Jan 23, 2002 Issued
10/044162 Plastic package with exposed die and method of making same Jan 10, 2002 Abandoned
Array ( [id] => 6761456 [patent_doc_number] => 20030124818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Method and apparatus for forming silicon containing films' [patent_app_type] => new [patent_app_number] => 10/040583 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10015 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124818.pdf [firstpage_image] =>[orig_patent_app_number] => 10040583 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040583
Method and apparatus for forming silicon containing films Dec 27, 2001 Abandoned
Array ( [id] => 1235564 [patent_doc_number] => 06689631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Semiconductor light-emitting device with improved electro-optical characteristics and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/014884 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4595 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/689/06689631.pdf [firstpage_image] =>[orig_patent_app_number] => 10014884 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/014884
Semiconductor light-emitting device with improved electro-optical characteristics and method of manufacturing the same Dec 13, 2001 Issued
Array ( [id] => 5787445 [patent_doc_number] => 20020160588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'METHOD OF FORMING A JUNCTION IN SEMICONDUCTOR DEVICE USING HALO IMPLANT PROCESSING' [patent_app_type] => new [patent_app_number] => 09/998134 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2042 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20020160588.pdf [firstpage_image] =>[orig_patent_app_number] => 09998134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/998134
METHOD OF FORMING A JUNCTION IN SEMICONDUCTOR DEVICE USING HALO IMPLANT PROCESSING Dec 2, 2001 Abandoned
Array ( [id] => 6290411 [patent_doc_number] => 20020055226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Method of forming a three-dimensional polysilicon layer on a semiconductor wafer' [patent_app_type] => new [patent_app_number] => 09/683213 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 2896 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055226.pdf [firstpage_image] =>[orig_patent_app_number] => 09683213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683213
Method of forming a three-dimensional polysilicon layer on a semiconductor wafer Dec 2, 2001 Issued
Array ( [id] => 662730 [patent_doc_number] => 07101771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Spin coating for maximum fill characteristic yielding a planarized thin film surface' [patent_app_type] => utility [patent_app_number] => 09/996423 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 7045 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/101/07101771.pdf [firstpage_image] =>[orig_patent_app_number] => 09996423 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996423
Spin coating for maximum fill characteristic yielding a planarized thin film surface Nov 27, 2001 Issued
Array ( [id] => 1358536 [patent_doc_number] => 06573143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Trench transistor structure and formation method' [patent_app_type] => B1 [patent_app_number] => 09/997324 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3440 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573143.pdf [firstpage_image] =>[orig_patent_app_number] => 09997324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/997324
Trench transistor structure and formation method Nov 27, 2001 Issued
Array ( [id] => 7221352 [patent_doc_number] => 20050260835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-24 [patent_title] => 'Sheet type heat treating device and method for processing semiconductors' [patent_app_type] => utility [patent_app_number] => 10/466113 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20050260835.pdf [firstpage_image] =>[orig_patent_app_number] => 10466113 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/466113
Sheet type heat treating apparatus and method for processing semiconductors Nov 26, 2001 Issued
Array ( [id] => 6130044 [patent_doc_number] => 20020076867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Method of forming a metal gate in a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/994284 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2783 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20020076867.pdf [firstpage_image] =>[orig_patent_app_number] => 09994284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994284
Method of forming a metal gate in a semiconductor device Nov 25, 2001 Issued
Array ( [id] => 6327515 [patent_doc_number] => 20020197858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Method for fabricating semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/990214 [patent_app_country] => US [patent_app_date] => 2001-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1303 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20020197858.pdf [firstpage_image] =>[orig_patent_app_number] => 09990214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/990214
Method for fabricating semiconductor devices Nov 20, 2001 Abandoned
Array ( [id] => 1595588 [patent_doc_number] => 06492243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Methods of forming capacitors and resultant capacitor structures' [patent_app_type] => B2 [patent_app_number] => 09/990715 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3191 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492243.pdf [firstpage_image] =>[orig_patent_app_number] => 09990715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/990715
Methods of forming capacitors and resultant capacitor structures Nov 19, 2001 Issued
Array ( [id] => 1277741 [patent_doc_number] => 06645815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Method for forming trench MOSFET device with low parasitic resistance' [patent_app_type] => B2 [patent_app_number] => 10/010483 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4748 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645815.pdf [firstpage_image] =>[orig_patent_app_number] => 10010483 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010483
Method for forming trench MOSFET device with low parasitic resistance Nov 19, 2001 Issued
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