Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1297542 [patent_doc_number] => 06627537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Bit line and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/777703 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2962 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627537.pdf [firstpage_image] =>[orig_patent_app_number] => 09777703 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777703
Bit line and manufacturing method thereof Feb 6, 2001 Issued
Array ( [id] => 1396333 [patent_doc_number] => 06531347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method of making recessed source drains to reduce fringing capacitance' [patent_app_type] => B1 [patent_app_number] => 09/776713 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3255 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531347.pdf [firstpage_image] =>[orig_patent_app_number] => 09776713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776713
Method of making recessed source drains to reduce fringing capacitance Feb 5, 2001 Issued
Array ( [id] => 6876694 [patent_doc_number] => 20010006847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Method for contact size control for nand technology' [patent_app_type] => new-utility [patent_app_number] => 09/775723 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3508 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006847.pdf [firstpage_image] =>[orig_patent_app_number] => 09775723 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775723
Method for contact size control for nand technology Jan 31, 2001 Abandoned
Array ( [id] => 6877573 [patent_doc_number] => 20010003059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new-utility [patent_app_number] => 09/770494 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 20598 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003059.pdf [firstpage_image] =>[orig_patent_app_number] => 09770494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770494
Method of manufacturing a ball grid array type semiconductor package Jan 28, 2001 Issued
Array ( [id] => 1360031 [patent_doc_number] => 06576940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'Semiconductor device having a solid state image sensing device and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/768233 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7119 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576940.pdf [firstpage_image] =>[orig_patent_app_number] => 09768233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/768233
Semiconductor device having a solid state image sensing device and manufacturing method thereof Jan 24, 2001 Issued
Array ( [id] => 6888501 [patent_doc_number] => 20010023956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Process of manufacturing a dram cell capacitor having increased trench capacitance' [patent_app_type] => new [patent_app_number] => 09/767634 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3986 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023956.pdf [firstpage_image] =>[orig_patent_app_number] => 09767634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767634
Process of manufacturing a DRAM cell capacitor having increased trench capacitance Jan 22, 2001 Issued
Array ( [id] => 7000483 [patent_doc_number] => 20010053559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Method of fabricating display device' [patent_app_type] => new [patent_app_number] => 09/768133 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8595 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053559.pdf [firstpage_image] =>[orig_patent_app_number] => 09768133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/768133
Method of fabricating display device Jan 22, 2001 Abandoned
Array ( [id] => 6878166 [patent_doc_number] => 20010002321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-31 [patent_title] => 'Ball grid substrate for lead-on-chip semiconductor package' [patent_app_type] => new-utility [patent_app_number] => 09/765004 [patent_app_country] => US [patent_app_date] => 2001-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4826 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002321.pdf [firstpage_image] =>[orig_patent_app_number] => 09765004 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765004
Ball grid substrate for lead-on-chip semiconductor package Jan 17, 2001 Issued
Array ( [id] => 7118464 [patent_doc_number] => 20010001744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new-utility [patent_app_number] => 09/739888 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6868 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001744.pdf [firstpage_image] =>[orig_patent_app_number] => 09739888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739888
Semiconductor device and method of manufacturing the same Dec 19, 2000 Abandoned
Array ( [id] => 7051960 [patent_doc_number] => 20010001292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-17 [patent_title] => 'Through-chip conductors for low inductance chip-to-chip integration and off-chip connections' [patent_app_type] => new-utility [patent_app_number] => 09/746534 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4218 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001292.pdf [firstpage_image] =>[orig_patent_app_number] => 09746534 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746534
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections Dec 18, 2000 Issued
Array ( [id] => 6877564 [patent_doc_number] => 20010003050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => new-utility [patent_app_number] => 09/726054 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12823 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003050.pdf [firstpage_image] =>[orig_patent_app_number] => 09726054 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/726054
Method of fabricating semiconductor device Nov 29, 2000 Issued
Array ( [id] => 6878165 [patent_doc_number] => 20010002320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-31 [patent_title] => 'Extended lead package' [patent_app_type] => new-utility [patent_app_number] => 09/726260 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002320.pdf [firstpage_image] =>[orig_patent_app_number] => 09726260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/726260
Extended lead package Nov 29, 2000 Abandoned
Array ( [id] => 1422043 [patent_doc_number] => 06518600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Dual encapsulation for an LED' [patent_app_type] => B1 [patent_app_number] => 09/714434 [patent_app_country] => US [patent_app_date] => 2000-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4829 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518600.pdf [firstpage_image] =>[orig_patent_app_number] => 09714434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/714434
Dual encapsulation for an LED Nov 16, 2000 Issued
Array ( [id] => 1386456 [patent_doc_number] => 06548395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method of promoting void free copper interconnects' [patent_app_type] => B1 [patent_app_number] => 09/713313 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548395.pdf [firstpage_image] =>[orig_patent_app_number] => 09713313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713313
Method of promoting void free copper interconnects Nov 15, 2000 Issued
Array ( [id] => 1550505 [patent_doc_number] => 06399496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Copper interconnection structure incorporating a metal seed layer' [patent_app_type] => B1 [patent_app_number] => 09/714504 [patent_app_country] => US [patent_app_date] => 2000-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5764 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399496.pdf [firstpage_image] =>[orig_patent_app_number] => 09714504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/714504
Copper interconnection structure incorporating a metal seed layer Nov 15, 2000 Issued
Array ( [id] => 1141370 [patent_doc_number] => 06777275 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Single anneal for dopant activation and silicide formation' [patent_app_type] => B1 [patent_app_number] => 09/712234 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 3717 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777275.pdf [firstpage_image] =>[orig_patent_app_number] => 09712234 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712234
Single anneal for dopant activation and silicide formation Nov 14, 2000 Issued
Array ( [id] => 1424569 [patent_doc_number] => 06503833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby' [patent_app_type] => B1 [patent_app_number] => 09/712264 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3708 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503833.pdf [firstpage_image] =>[orig_patent_app_number] => 09712264 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712264
Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby Nov 14, 2000 Issued
Array ( [id] => 1580211 [patent_doc_number] => 06448600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'DRAM cell configuration and fabrication method' [patent_app_type] => B1 [patent_app_number] => 09/713484 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448600.pdf [firstpage_image] =>[orig_patent_app_number] => 09713484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713484
DRAM cell configuration and fabrication method Nov 14, 2000 Issued
Array ( [id] => 1490160 [patent_doc_number] => 06417052 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Fabrication process for semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/712243 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 44 [patent_no_of_words] => 9398 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417052.pdf [firstpage_image] =>[orig_patent_app_number] => 09712243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/712243
Fabrication process for semiconductor device Nov 14, 2000 Issued
Array ( [id] => 1376538 [patent_doc_number] => 06559062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for avoiding notching in a semiconductor interconnect during a metal etching step' [patent_app_type] => B1 [patent_app_number] => 09/713504 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3815 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559062.pdf [firstpage_image] =>[orig_patent_app_number] => 09713504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/713504
Method for avoiding notching in a semiconductor interconnect during a metal etching step Nov 14, 2000 Issued
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