
Tanya Theresa Ngo Motsinger
Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )
| Most Active Art Unit | 2637 |
| Art Unit(s) | 2635, 2613, 2637 |
| Total Applications | 469 |
| Issued Applications | 358 |
| Pending Applications | 25 |
| Abandoned Applications | 99 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1297542
[patent_doc_number] => 06627537
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-30
[patent_title] => 'Bit line and manufacturing method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/777703
[patent_app_country] => US
[patent_app_date] => 2001-02-07
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/627/06627537.pdf
[firstpage_image] =>[orig_patent_app_number] => 09777703
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/777703 | Bit line and manufacturing method thereof | Feb 6, 2001 | Issued |
Array
(
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[patent_doc_number] => 06531347
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-03-11
[patent_title] => 'Method of making recessed source drains to reduce fringing capacitance'
[patent_app_type] => B1
[patent_app_number] => 09/776713
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/776713 | Method of making recessed source drains to reduce fringing capacitance | Feb 5, 2001 | Issued |
Array
(
[id] => 6876694
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[patent_issue_date] => 2001-07-05
[patent_title] => 'Method for contact size control for nand technology'
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[patent_app_number] => 09/775723
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[patent_app_date] => 2001-02-01
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Array
(
[id] => 6877573
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[patent_issue_date] => 2001-06-07
[patent_title] => 'Semiconductor device and manufacturing method thereof'
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[patent_app_number] => 09/770494
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[patent_app_date] => 2001-01-29
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[firstpage_image] =>[orig_patent_app_number] => 09770494
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/770494 | Method of manufacturing a ball grid array type semiconductor package | Jan 28, 2001 | Issued |
Array
(
[id] => 1360031
[patent_doc_number] => 06576940
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[patent_issue_date] => 2003-06-10
[patent_title] => 'Semiconductor device having a solid state image sensing device and manufacturing method thereof'
[patent_app_type] => B2
[patent_app_number] => 09/768233
[patent_app_country] => US
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[pdf_file] => patents/06/576/06576940.pdf
[firstpage_image] =>[orig_patent_app_number] => 09768233
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768233 | Semiconductor device having a solid state image sensing device and manufacturing method thereof | Jan 24, 2001 | Issued |
Array
(
[id] => 6888501
[patent_doc_number] => 20010023956
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[patent_issue_date] => 2001-09-27
[patent_title] => 'Process of manufacturing a dram cell capacitor having increased trench capacitance'
[patent_app_type] => new
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Array
(
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[patent_title] => 'Method of fabricating display device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/768133 | Method of fabricating display device | Jan 22, 2001 | Abandoned |
Array
(
[id] => 6878166
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[patent_title] => 'Ball grid substrate for lead-on-chip semiconductor package'
[patent_app_type] => new-utility
[patent_app_number] => 09/765004
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[patent_app_date] => 2001-01-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/765004 | Ball grid substrate for lead-on-chip semiconductor package | Jan 17, 2001 | Issued |
Array
(
[id] => 7118464
[patent_doc_number] => 20010001744
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/739888 | Semiconductor device and method of manufacturing the same | Dec 19, 2000 | Abandoned |
Array
(
[id] => 7051960
[patent_doc_number] => 20010001292
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[patent_kind] => A1
[patent_issue_date] => 2001-05-17
[patent_title] => 'Through-chip conductors for low inductance chip-to-chip integration and off-chip connections'
[patent_app_type] => new-utility
[patent_app_number] => 09/746534
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Array
(
[id] => 6877564
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[patent_title] => 'Method of fabricating semiconductor device'
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Array
(
[id] => 6878165
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[patent_title] => 'Extended lead package'
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Array
(
[id] => 1422043
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[patent_title] => 'Dual encapsulation for an LED'
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Array
(
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[patent_title] => 'Method of promoting void free copper interconnects'
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Array
(
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Array
(
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[patent_title] => 'Single anneal for dopant activation and silicide formation'
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Array
(
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Array
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Array
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Array
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