Search

Tanya Theresa Ngo Motsinger

Examiner (ID: 10491, Phone: (571)270-7488 , Office: P/2637 )

Most Active Art Unit
2637
Art Unit(s)
2635, 2613, 2637
Total Applications
469
Issued Applications
358
Pending Applications
25
Abandoned Applications
99

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4258765 [patent_doc_number] => 06258661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Formation of out-diffused bitline by laser anneal' [patent_app_type] => 1 [patent_app_number] => 9/651614 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 4135 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258661.pdf [firstpage_image] =>[orig_patent_app_number] => 651614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651614
Formation of out-diffused bitline by laser anneal Aug 29, 2000 Issued
Array ( [id] => 1433322 [patent_doc_number] => 06340612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method of fabricating body contacted and backgated transistors' [patent_app_type] => B1 [patent_app_number] => 09/649983 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 7549 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340612.pdf [firstpage_image] =>[orig_patent_app_number] => 09649983 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/649983
Method of fabricating body contacted and backgated transistors Aug 28, 2000 Issued
Array ( [id] => 4328526 [patent_doc_number] => 06312964 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Circuit, structure and method of testing a semiconductor, such as an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/648221 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5165 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/312/06312964.pdf [firstpage_image] =>[orig_patent_app_number] => 648221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648221
Circuit, structure and method of testing a semiconductor, such as an integrated circuit Aug 24, 2000 Issued
Array ( [id] => 1594601 [patent_doc_number] => 06383923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Article comprising vertically nano-interconnected circuit devices and method for making the same' [patent_app_type] => B1 [patent_app_number] => 09/643784 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5957 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383923.pdf [firstpage_image] =>[orig_patent_app_number] => 09643784 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643784
Article comprising vertically nano-interconnected circuit devices and method for making the same Aug 21, 2000 Issued
Array ( [id] => 4270615 [patent_doc_number] => 06323057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method of producing a thin-film capacitor' [patent_app_type] => 1 [patent_app_number] => 9/635174 [patent_app_country] => US [patent_app_date] => 2000-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5811 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323057.pdf [firstpage_image] =>[orig_patent_app_number] => 635174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/635174
Method of producing a thin-film capacitor Aug 8, 2000 Issued
Array ( [id] => 1517373 [patent_doc_number] => 06500759 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Protective layer having compression stress on titanium layer in method of making a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/554906 [patent_app_country] => US [patent_app_date] => 2000-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4215 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500759.pdf [firstpage_image] =>[orig_patent_app_number] => 09554906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/554906
Protective layer having compression stress on titanium layer in method of making a semiconductor device Aug 7, 2000 Issued
Array ( [id] => 1412938 [patent_doc_number] => 06524967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method for incorporating nitrogen into a dielectric layer using a special precursor' [patent_app_type] => B1 [patent_app_number] => 09/630083 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2909 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524967.pdf [firstpage_image] =>[orig_patent_app_number] => 09630083 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/630083
Method for incorporating nitrogen into a dielectric layer using a special precursor Jul 31, 2000 Issued
Array ( [id] => 4310139 [patent_doc_number] => 06316309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Method of forming self-isolated and self-aligned 4F-square vertical FET-trench DRAM cells' [patent_app_type] => 1 [patent_app_number] => 9/626332 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 5071 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316309.pdf [firstpage_image] =>[orig_patent_app_number] => 626332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626332
Method of forming self-isolated and self-aligned 4F-square vertical FET-trench DRAM cells Jul 25, 2000 Issued
Array ( [id] => 1458820 [patent_doc_number] => 06426274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method for making thin film semiconductor' [patent_app_type] => B1 [patent_app_number] => 09/616613 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 85 [patent_no_of_words] => 25180 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426274.pdf [firstpage_image] =>[orig_patent_app_number] => 09616613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/616613
Method for making thin film semiconductor Jul 13, 2000 Issued
Array ( [id] => 4326332 [patent_doc_number] => 06319754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Wafer-dicing process' [patent_app_type] => 1 [patent_app_number] => 9/613553 [patent_app_country] => US [patent_app_date] => 2000-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1722 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319754.pdf [firstpage_image] =>[orig_patent_app_number] => 613553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/613553
Wafer-dicing process Jul 9, 2000 Issued
Array ( [id] => 1494892 [patent_doc_number] => 06403430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor structure having more usable substrate area and method for forming same' [patent_app_type] => B1 [patent_app_number] => 09/613003 [patent_app_country] => US [patent_app_date] => 2000-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403430.pdf [firstpage_image] =>[orig_patent_app_number] => 09613003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/613003
Semiconductor structure having more usable substrate area and method for forming same Jul 9, 2000 Issued
Array ( [id] => 1433318 [patent_doc_number] => 06340608 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads' [patent_app_type] => B1 [patent_app_number] => 09/612564 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 1612 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340608.pdf [firstpage_image] =>[orig_patent_app_number] => 09612564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/612564
Method of fabricating copper metal bumps for flip-chip or chip-on-board IC bonding on terminating copper pads Jul 6, 2000 Issued
Array ( [id] => 1507229 [patent_doc_number] => 06440766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Microfabrication using germanium-based release masks' [patent_app_type] => B1 [patent_app_number] => 09/612563 [patent_app_country] => US [patent_app_date] => 2000-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 3996 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440766.pdf [firstpage_image] =>[orig_patent_app_number] => 09612563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/612563
Microfabrication using germanium-based release masks Jul 6, 2000 Issued
Array ( [id] => 1553453 [patent_doc_number] => 06348370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method to fabricate a self aligned source resistor in embedded flash memory applications' [patent_app_type] => B1 [patent_app_number] => 09/610274 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4831 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348370.pdf [firstpage_image] =>[orig_patent_app_number] => 09610274 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/610274
Method to fabricate a self aligned source resistor in embedded flash memory applications Jul 5, 2000 Issued
Array ( [id] => 1550337 [patent_doc_number] => 06399450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions' [patent_app_type] => B1 [patent_app_number] => 09/609613 [patent_app_country] => US [patent_app_date] => 2000-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3602 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399450.pdf [firstpage_image] =>[orig_patent_app_number] => 09609613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609613
Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions Jul 4, 2000 Issued
Array ( [id] => 4325629 [patent_doc_number] => 06329306 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Fine patterning utilizing an exposure method in photolithography' [patent_app_type] => 1 [patent_app_number] => 9/609944 [patent_app_country] => US [patent_app_date] => 2000-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5385 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329306.pdf [firstpage_image] =>[orig_patent_app_number] => 609944 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609944
Fine patterning utilizing an exposure method in photolithography Jul 2, 2000 Issued
Array ( [id] => 1505312 [patent_doc_number] => 06465823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Dynamic threshold voltage metal insulator semiconductor effect transistor' [patent_app_type] => B1 [patent_app_number] => 09/609713 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 172 [patent_no_of_words] => 15851 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465823.pdf [firstpage_image] =>[orig_patent_app_number] => 09609713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609713
Dynamic threshold voltage metal insulator semiconductor effect transistor Jun 29, 2000 Issued
Array ( [id] => 1544644 [patent_doc_number] => 06444405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductors substrate' [patent_app_type] => B1 [patent_app_number] => 09/610114 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 58 [patent_no_of_words] => 14982 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444405.pdf [firstpage_image] =>[orig_patent_app_number] => 09610114 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/610114
Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductors substrate Jun 29, 2000 Issued
Array ( [id] => 1435850 [patent_doc_number] => 06355493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Method for forming IC\'s comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon' [patent_app_type] => B1 [patent_app_number] => 09/609074 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5530 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355493.pdf [firstpage_image] =>[orig_patent_app_number] => 09609074 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609074
Method for forming IC's comprising a highly-resistive or semi-insulating semiconductor substrate having a thin, low resistance active semiconductor layer thereon Jun 29, 2000 Issued
Array ( [id] => 1446579 [patent_doc_number] => 06368927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method of manufacturing transistor having elevated source and drain regions' [patent_app_type] => B1 [patent_app_number] => 09/608064 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2544 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368927.pdf [firstpage_image] =>[orig_patent_app_number] => 09608064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608064
Method of manufacturing transistor having elevated source and drain regions Jun 28, 2000 Issued
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