Tao Peng
Examiner (ID: 17961, Phone: (571)431-0711 , Office: P/2121 )
Most Active Art Unit | 2121 |
Art Unit(s) | 2121, 4141, 2126 |
Total Applications | 12 |
Issued Applications | 1 |
Pending Applications | 0 |
Abandoned Applications | 11 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 8114471
[patent_doc_number] => 08158452
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-17
[patent_title] => 'Backside-illuminated imaging device and manufacturing method of the same'
[patent_app_type] => utility
[patent_app_number] => 13/007482
[patent_app_country] => US
[patent_app_date] => 2011-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 5098
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/158/08158452.pdf
[firstpage_image] =>[orig_patent_app_number] => 13007482
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/007482 | Backside-illuminated imaging device and manufacturing method of the same | Jan 13, 2011 | Issued |
Array
(
[id] => 8028107
[patent_doc_number] => 08143136
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-27
[patent_title] => 'Method for fabricating crown-shaped capacitor'
[patent_app_type] => utility
[patent_app_number] => 12/979775
[patent_app_country] => US
[patent_app_date] => 2010-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3822
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 288
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/143/08143136.pdf
[firstpage_image] =>[orig_patent_app_number] => 12979775
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/979775 | Method for fabricating crown-shaped capacitor | Dec 27, 2010 | Issued |
Array
(
[id] => 7703379
[patent_doc_number] => 08089136
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-03
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/891214
[patent_app_country] => US
[patent_app_date] => 2010-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 7647
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/089/08089136.pdf
[firstpage_image] =>[orig_patent_app_number] => 12891214
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/891214 | Semiconductor device | Sep 26, 2010 | Issued |
Array
(
[id] => 7762167
[patent_doc_number] => 08114763
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-14
[patent_title] => 'Tantalum aluminum oxynitride high-K dielectric'
[patent_app_type] => utility
[patent_app_number] => 12/838983
[patent_app_country] => US
[patent_app_date] => 2010-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 16806
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/114/08114763.pdf
[firstpage_image] =>[orig_patent_app_number] => 12838983
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/838983 | Tantalum aluminum oxynitride high-K dielectric | Jul 18, 2010 | Issued |
Array
(
[id] => 6293091
[patent_doc_number] => 20100159657
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-24
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/715964
[patent_app_country] => US
[patent_app_date] => 2010-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 53
[patent_figures_cnt] => 53
[patent_no_of_words] => 10481
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0159/20100159657.pdf
[firstpage_image] =>[orig_patent_app_number] => 12715964
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/715964 | Semiconductor memory device and method of fabricating the same | Mar 1, 2010 | Issued |
Array
(
[id] => 8005765
[patent_doc_number] => 08084283
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-27
[patent_title] => 'Top contact LED thermal management'
[patent_app_type] => utility
[patent_app_number] => 12/699709
[patent_app_country] => US
[patent_app_date] => 2010-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3846
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/084/08084283.pdf
[firstpage_image] =>[orig_patent_app_number] => 12699709
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/699709 | Top contact LED thermal management | Feb 2, 2010 | Issued |
Array
(
[id] => 6422406
[patent_doc_number] => 20100102347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-29
[patent_title] => 'LIGHT-EMITTING DIODE'
[patent_app_type] => utility
[patent_app_number] => 12/582924
[patent_app_country] => US
[patent_app_date] => 2009-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3854
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20100102347.pdf
[firstpage_image] =>[orig_patent_app_number] => 12582924
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/582924 | Light-emitting diode | Oct 20, 2009 | Issued |
Array
(
[id] => 8018115
[patent_doc_number] => 08138562
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-20
[patent_title] => 'Bit line preparation method in MRAM fabrication'
[patent_app_type] => utility
[patent_app_number] => 12/589193
[patent_app_country] => US
[patent_app_date] => 2009-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 7626
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/138/08138562.pdf
[firstpage_image] =>[orig_patent_app_number] => 12589193
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/589193 | Bit line preparation method in MRAM fabrication | Oct 19, 2009 | Issued |
Array
(
[id] => 4605028
[patent_doc_number] => 07986009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production'
[patent_app_type] => utility
[patent_app_number] => 12/511845
[patent_app_country] => US
[patent_app_date] => 2009-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5645
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/986/07986009.pdf
[firstpage_image] =>[orig_patent_app_number] => 12511845
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/511845 | Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production | Jul 28, 2009 | Issued |
Array
(
[id] => 4605028
[patent_doc_number] => 07986009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production'
[patent_app_type] => utility
[patent_app_number] => 12/511845
[patent_app_country] => US
[patent_app_date] => 2009-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5645
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/986/07986009.pdf
[firstpage_image] =>[orig_patent_app_number] => 12511845
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/511845 | Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production | Jul 28, 2009 | Issued |
Array
(
[id] => 4605028
[patent_doc_number] => 07986009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production'
[patent_app_type] => utility
[patent_app_number] => 12/511845
[patent_app_country] => US
[patent_app_date] => 2009-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5645
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/986/07986009.pdf
[firstpage_image] =>[orig_patent_app_number] => 12511845
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/511845 | Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production | Jul 28, 2009 | Issued |
Array
(
[id] => 4605028
[patent_doc_number] => 07986009
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-26
[patent_title] => 'Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production'
[patent_app_type] => utility
[patent_app_number] => 12/511845
[patent_app_country] => US
[patent_app_date] => 2009-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5645
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/986/07986009.pdf
[firstpage_image] =>[orig_patent_app_number] => 12511845
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/511845 | Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production | Jul 28, 2009 | Issued |
Array
(
[id] => 5401370
[patent_doc_number] => 20090236683
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-24
[patent_title] => 'Isolation structures for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 12/455212
[patent_app_country] => US
[patent_app_date] => 2009-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 14662
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0236/20090236683.pdf
[firstpage_image] =>[orig_patent_app_number] => 12455212
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/455212 | Isolation structures for integrated circuits | May 27, 2009 | Issued |
Array
(
[id] => 5441464
[patent_doc_number] => 20090093103
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-09
[patent_title] => 'Method and device for controlled cleaving process'
[patent_app_type] => utility
[patent_app_number] => 12/316172
[patent_app_country] => US
[patent_app_date] => 2008-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8690
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0093/20090093103.pdf
[firstpage_image] =>[orig_patent_app_number] => 12316172
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/316172 | Method and device for controlled cleaving process | Dec 8, 2008 | Abandoned |
Array
(
[id] => 5271659
[patent_doc_number] => 20090075435
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-19
[patent_title] => 'JFET With Built In Back Gate in Either SOI or Bulk Silicon'
[patent_app_type] => utility
[patent_app_number] => 12/270964
[patent_app_country] => US
[patent_app_date] => 2008-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8362
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0075/20090075435.pdf
[firstpage_image] =>[orig_patent_app_number] => 12270964
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/270964 | JFET with built in back gate in either SOI or bulk silicon | Nov 13, 2008 | Issued |
Array
(
[id] => 5444188
[patent_doc_number] => 20090045414
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'SILICON CARBIDE SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING THE SAME, AND SILICON CARBIDE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/193291
[patent_app_country] => US
[patent_app_date] => 2008-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4936
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0045/20090045414.pdf
[firstpage_image] =>[orig_patent_app_number] => 12193291
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/193291 | Silicon carbide semiconductor element, method of manufacturing the same, and silicon carbide device | Aug 17, 2008 | Issued |
Array
(
[id] => 6600060
[patent_doc_number] => 20100032761
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-11
[patent_title] => 'SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 12/188381
[patent_app_country] => US
[patent_app_date] => 2008-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 11199
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20100032761.pdf
[firstpage_image] =>[orig_patent_app_number] => 12188381
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/188381 | Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate | Aug 7, 2008 | Issued |
Array
(
[id] => 5319716
[patent_doc_number] => 20090057706
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'SET OF OHMIC CONTACT ELECTRODES ON BOTH P-TYPE AND N-TYPE LAYERS FOR GAN-BASED LED AND METHOD FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/184172
[patent_app_country] => US
[patent_app_date] => 2008-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4102
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0057/20090057706.pdf
[firstpage_image] =>[orig_patent_app_number] => 12184172
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/184172 | SET OF OHMIC CONTACT ELECTRODES ON BOTH P-TYPE AND N-TYPE LAYERS FOR GAN-BASED LED AND METHOD FOR FABRICATING THE SAME | Jul 30, 2008 | Abandoned |
Array
(
[id] => 7997959
[patent_doc_number] => 08080827
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-20
[patent_title] => 'Top contact LED thermal management'
[patent_app_type] => utility
[patent_app_number] => 12/183772
[patent_app_country] => US
[patent_app_date] => 2008-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3787
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/080/08080827.pdf
[firstpage_image] =>[orig_patent_app_number] => 12183772
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/183772 | Top contact LED thermal management | Jul 30, 2008 | Issued |
Array
(
[id] => 132793
[patent_doc_number] => 07701033
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-20
[patent_title] => 'Isolation structures for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 12/220986
[patent_app_country] => US
[patent_app_date] => 2008-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 67
[patent_no_of_words] => 14610
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/701/07701033.pdf
[firstpage_image] =>[orig_patent_app_number] => 12220986
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/220986 | Isolation structures for integrated circuits | Jul 29, 2008 | Issued |