Search

Tao Peng

Examiner (ID: 17961, Phone: (571)431-0711 , Office: P/2121 )

Most Active Art Unit
2121
Art Unit(s)
2121, 4141, 2126
Total Applications
12
Issued Applications
1
Pending Applications
0
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4715360 [patent_doc_number] => 20080237882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Annular via drilling (AVD) technology' [patent_app_type] => utility [patent_app_number] => 11/731432 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1921 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237882.pdf [firstpage_image] =>[orig_patent_app_number] => 11731432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/731432
Annular via drilling (AVD) technology Mar 29, 2007 Abandoned
Array ( [id] => 4958021 [patent_doc_number] => 20080272445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'LOW-K DISPLACER FOR OVERLAP CAPACITANCE REDUCTION' [patent_app_type] => utility [patent_app_number] => 11/687865 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6446 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20080272445.pdf [firstpage_image] =>[orig_patent_app_number] => 11687865 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/687865
LOW-K DISPLACER FOR OVERLAP CAPACITANCE REDUCTION Mar 18, 2007 Abandoned
Array ( [id] => 132756 [patent_doc_number] => 07701017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'MOS semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/674356 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 14582 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/701/07701017.pdf [firstpage_image] =>[orig_patent_app_number] => 11674356 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/674356
MOS semiconductor device and method of fabricating the same Feb 12, 2007 Issued
Array ( [id] => 334619 [patent_doc_number] => 07508031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Enhanced segmented channel MOS transistor with narrowed base regions' [patent_app_type] => utility [patent_app_number] => 11/668756 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 42 [patent_no_of_words] => 15914 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/508/07508031.pdf [firstpage_image] =>[orig_patent_app_number] => 11668756 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/668756
Enhanced segmented channel MOS transistor with narrowed base regions Jan 29, 2007 Issued
Array ( [id] => 4890695 [patent_doc_number] => 20080099792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'MEMORY DEVICES AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/616402 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5429 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20080099792.pdf [firstpage_image] =>[orig_patent_app_number] => 11616402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616402
Memory devices including spacers of different materials Dec 26, 2006 Issued
Array ( [id] => 133813 [patent_doc_number] => 07696559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Semiconductor memory device including pillar-shaped semiconductor layers and a method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/616522 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 65 [patent_no_of_words] => 10466 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/696/07696559.pdf [firstpage_image] =>[orig_patent_app_number] => 11616522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616522
Semiconductor memory device including pillar-shaped semiconductor layers and a method of fabricating the same Dec 26, 2006 Issued
Array ( [id] => 5022978 [patent_doc_number] => 20070148944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Interconnection of Semiconductor Device and Method for Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 11/613512 [patent_app_country] => US [patent_app_date] => 2006-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2385 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148944.pdf [firstpage_image] =>[orig_patent_app_number] => 11613512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/613512
Interconnection of Semiconductor Device and Method for Manufacturing the Same Dec 19, 2006 Abandoned
Array ( [id] => 8375255 [patent_doc_number] => 08258047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Nanostructures, methods of depositing nanostructures and devices incorporating the same' [patent_app_type] => utility [patent_app_number] => 11/633205 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3682 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11633205 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/633205
Nanostructures, methods of depositing nanostructures and devices incorporating the same Dec 3, 2006 Issued
Array ( [id] => 4829267 [patent_doc_number] => 20080128797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'STRUCTURE AND METHOD FOR MULTIPLE HEIGHT FINFET DEVICES' [patent_app_type] => utility [patent_app_number] => 11/565136 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6550 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128797.pdf [firstpage_image] =>[orig_patent_app_number] => 11565136 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565136
STRUCTURE AND METHOD FOR MULTIPLE HEIGHT FINFET DEVICES Nov 29, 2006 Abandoned
Array ( [id] => 5104398 [patent_doc_number] => 20070063273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/600062 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10668 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20070063273.pdf [firstpage_image] =>[orig_patent_app_number] => 11600062 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/600062
Semiconductor device and method for manufacturing the same Nov 15, 2006 Abandoned
Array ( [id] => 5168837 [patent_doc_number] => 20070069268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'RECESSED GATE TRANSISTOR STRUCTURE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/560756 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3749 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20070069268.pdf [firstpage_image] =>[orig_patent_app_number] => 11560756 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560756
Recessed gate transistor structure and method of forming the same Nov 15, 2006 Issued
Array ( [id] => 4901751 [patent_doc_number] => 20080111163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'FIELD EFFECT TRANSISTOR WITH A FIN STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/559656 [patent_app_country] => US [patent_app_date] => 2006-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16875 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 57 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111163.pdf [firstpage_image] =>[orig_patent_app_number] => 11559656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/559656
Field effect transistor with a fin structure Nov 13, 2006 Issued
Array ( [id] => 4820789 [patent_doc_number] => 20080122060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING CORROSION RESISTANT WIRING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/558056 [patent_app_country] => US [patent_app_date] => 2006-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3204 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122060.pdf [firstpage_image] =>[orig_patent_app_number] => 11558056 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/558056
SEMICONDUCTOR DEVICE INCLUDING CORROSION RESISTANT WIRING STRUCTURE Nov 8, 2006 Abandoned
Array ( [id] => 4829212 [patent_doc_number] => 20080128762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Junction isolated poly-silicon gate JFET' [patent_app_type] => utility [patent_app_number] => 11/590376 [patent_app_country] => US [patent_app_date] => 2006-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8811 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128762.pdf [firstpage_image] =>[orig_patent_app_number] => 11590376 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590376
Junction isolated poly-silicon gate JFET Oct 30, 2006 Abandoned
Array ( [id] => 4997551 [patent_doc_number] => 20070040185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Semiconductor device and capacitance regulation circuit' [patent_app_type] => utility [patent_app_number] => 11/589172 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10172 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040185.pdf [firstpage_image] =>[orig_patent_app_number] => 11589172 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/589172
Semiconductor device and capacitance regulation circuit Oct 29, 2006 Abandoned
Array ( [id] => 4999946 [patent_doc_number] => 20070042580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'ION IMPLANTED INSULATOR MATERIAL WITH REDUCED DIELECTRIC CONSTANT' [patent_app_type] => utility [patent_app_number] => 11/551196 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9362 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20070042580.pdf [firstpage_image] =>[orig_patent_app_number] => 11551196 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/551196
ION IMPLANTED INSULATOR MATERIAL WITH REDUCED DIELECTRIC CONSTANT Oct 18, 2006 Abandoned
Array ( [id] => 5104386 [patent_doc_number] => 20070063261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Necked Finfet device' [patent_app_type] => utility [patent_app_number] => 11/548772 [patent_app_country] => US [patent_app_date] => 2006-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2898 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20070063261.pdf [firstpage_image] =>[orig_patent_app_number] => 11548772 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/548772
Necked Finfet device Oct 11, 2006 Abandoned
Array ( [id] => 4610277 [patent_doc_number] => 07994534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Organic light emitting display device and a method of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 11/540366 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8350 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/994/07994534.pdf [firstpage_image] =>[orig_patent_app_number] => 11540366 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540366
Organic light emitting display device and a method of manufacturing thereof Sep 28, 2006 Issued
Array ( [id] => 5239850 [patent_doc_number] => 20070018341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Contact etching utilizing partially recessed hard mask' [patent_app_type] => utility [patent_app_number] => 11/540392 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2597 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018341.pdf [firstpage_image] =>[orig_patent_app_number] => 11540392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540392
Contact etching utilizing partially recessed hard mask Sep 28, 2006 Abandoned
Array ( [id] => 4460245 [patent_doc_number] => 07879669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-01 [patent_title] => 'Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length' [patent_app_type] => utility [patent_app_number] => 11/527265 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 69 [patent_no_of_words] => 48393 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/879/07879669.pdf [firstpage_image] =>[orig_patent_app_number] => 11527265 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527265
Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length Sep 24, 2006 Issued
Menu