
Taqi R. Nasir
Examiner (ID: 2628, Phone: (571)270-1425 , Office: P/2858 )
| Most Active Art Unit | 2858 |
| Art Unit(s) | 2858 |
| Total Applications | 700 |
| Issued Applications | 579 |
| Pending Applications | 93 |
| Abandoned Applications | 67 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20223055
[patent_doc_number] => 20250285986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-11
[patent_title] => SCALABLE ELECTRONICS MANUFACTURING WITH RIGID TILE PANEL EMBEDDING
[patent_app_type] => utility
[patent_app_number] => 19/072087
[patent_app_country] => US
[patent_app_date] => 2025-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19072087
[rel_patent_id] =>[rel_patent_doc_number] =>) 19/072087 | SCALABLE ELECTRONICS MANUFACTURING WITH RIGID TILE PANEL EMBEDDING | Mar 5, 2025 | Pending |
Array
(
[id] => 20347609
[patent_doc_number] => 12471347
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Vertical power semiconductor device and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/969220
[patent_app_country] => US
[patent_app_date] => 2024-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 27
[patent_no_of_words] => 7888
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18969220
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/969220 | Vertical power semiconductor device and manufacturing method thereof | Dec 3, 2024 | Issued |
Array
(
[id] => 19407191
[patent_doc_number] => 20240290702
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/655879
[patent_app_country] => US
[patent_app_date] => 2024-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9551
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655879
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/655879 | INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME | May 5, 2024 | Pending |
Array
(
[id] => 19364248
[patent_doc_number] => 20240266282
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN VIA
[patent_app_type] => utility
[patent_app_number] => 18/640636
[patent_app_country] => US
[patent_app_date] => 2024-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19900
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640636
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/640636 | SEMICONDUCTOR DEVICE WITH SOURCE/DRAIN VIA | Apr 18, 2024 | Pending |
Array
(
[id] => 19269533
[patent_doc_number] => 20240213237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => INFO PACKAGES INCLUDING THERMAL DISSIPATION BLOCKS
[patent_app_type] => utility
[patent_app_number] => 18/602533
[patent_app_country] => US
[patent_app_date] => 2024-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9599
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602533
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/602533 | Info packages including thermal dissipation blocks | Mar 11, 2024 | Issued |
Array
(
[id] => 19269533
[patent_doc_number] => 20240213237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => INFO PACKAGES INCLUDING THERMAL DISSIPATION BLOCKS
[patent_app_type] => utility
[patent_app_number] => 18/602533
[patent_app_country] => US
[patent_app_date] => 2024-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9599
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18602533
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/602533 | Info packages including thermal dissipation blocks | Mar 11, 2024 | Issued |
Array
(
[id] => 19269401
[patent_doc_number] => 20240213105
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => MITIGATING SURFACE DAMAGE OF PROBE PADS IN PREPARATION FOR DIRECT BONDING OF A SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/600278
[patent_app_country] => US
[patent_app_date] => 2024-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4924
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600278
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/600278 | Mitigating surface damage of probe pads in preparation for direct bonding of a substrate | Mar 7, 2024 | Issued |
Array
(
[id] => 19943717
[patent_doc_number] => 12315854
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Integrated circuit package and method
[patent_app_type] => utility
[patent_app_number] => 18/593536
[patent_app_country] => US
[patent_app_date] => 2024-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 11195
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593536
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/593536 | Integrated circuit package and method | Feb 29, 2024 | Issued |
Array
(
[id] => 19901544
[patent_doc_number] => 12279498
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-15
[patent_title] => Organic light emitting diode display device including a power supply wire
[patent_app_type] => utility
[patent_app_number] => 18/544416
[patent_app_country] => US
[patent_app_date] => 2023-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10613
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544416
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/544416 | Organic light emitting diode display device including a power supply wire | Dec 17, 2023 | Issued |
Array
(
[id] => 19901544
[patent_doc_number] => 12279498
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-15
[patent_title] => Organic light emitting diode display device including a power supply wire
[patent_app_type] => utility
[patent_app_number] => 18/544416
[patent_app_country] => US
[patent_app_date] => 2023-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10613
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544416
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/544416 | Organic light emitting diode display device including a power supply wire | Dec 17, 2023 | Issued |
Array
(
[id] => 19087939
[patent_doc_number] => 20240114740
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-04
[patent_title] => Foldable Display Apparatus
[patent_app_type] => utility
[patent_app_number] => 18/521947
[patent_app_country] => US
[patent_app_date] => 2023-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8352
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18521947
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/521947 | Foldable Display Apparatus | Nov 27, 2023 | Pending |
Array
(
[id] => 18991307
[patent_doc_number] => 20240063276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/380754
[patent_app_country] => US
[patent_app_date] => 2023-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10766
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18380754
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/380754 | Semiconductor device and method for fabricating the same | Oct 16, 2023 | Issued |
Array
(
[id] => 18943590
[patent_doc_number] => 20240038729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-01
[patent_title] => DOUBLE-SIDED SUBSTRATE WITH CAVITIES FOR DIRECT DIE-TO-DIE INTERCONNECT
[patent_app_type] => utility
[patent_app_number] => 18/377639
[patent_app_country] => US
[patent_app_date] => 2023-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10670
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18377639
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/377639 | Double-sided substrate with cavities for direct die-to-die interconnect | Oct 5, 2023 | Issued |
Array
(
[id] => 18927112
[patent_doc_number] => 20240030116
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
[patent_app_type] => utility
[patent_app_number] => 18/375133
[patent_app_country] => US
[patent_app_date] => 2023-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10273
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18375133
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/375133 | Ultra-thin, hyper-density semiconductor packages | Sep 28, 2023 | Issued |
Array
(
[id] => 18927112
[patent_doc_number] => 20240030116
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
[patent_app_type] => utility
[patent_app_number] => 18/375133
[patent_app_country] => US
[patent_app_date] => 2023-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10273
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18375133
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/375133 | Ultra-thin, hyper-density semiconductor packages | Sep 28, 2023 | Issued |
Array
(
[id] => 19781586
[patent_doc_number] => 12230624
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Integrated circuit with mixed row heights
[patent_app_type] => utility
[patent_app_number] => 18/232759
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 17978
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232759
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/232759 | Integrated circuit with mixed row heights | Aug 9, 2023 | Issued |
Array
(
[id] => 19696491
[patent_doc_number] => 20250015036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-09
[patent_title] => PREFORMED UNIT OF FAN-OUT CHIP-EMBEDDED PACKAGING PROCESS AND APPLICATION MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/447466
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2060
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447466
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447466 | PREFORMED UNIT OF FAN-OUT CHIP-EMBEDDED PACKAGING PROCESS AND APPLICATION MANUFACTURING METHOD THEREOF | Aug 9, 2023 | Pending |
Array
(
[id] => 19696491
[patent_doc_number] => 20250015036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-09
[patent_title] => PREFORMED UNIT OF FAN-OUT CHIP-EMBEDDED PACKAGING PROCESS AND APPLICATION MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/447466
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2060
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447466
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447466 | PREFORMED UNIT OF FAN-OUT CHIP-EMBEDDED PACKAGING PROCESS AND APPLICATION MANUFACTURING METHOD THEREOF | Aug 9, 2023 | Pending |
Array
(
[id] => 18776389
[patent_doc_number] => 20230371227
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-16
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/361384
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11930
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361384
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361384 | Memory device | Jul 27, 2023 | Issued |
Array
(
[id] => 19007825
[patent_doc_number] => 20240071896
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/361482
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7344
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361482
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361482 | SEMICONDUCTOR PACKAGE | Jul 27, 2023 | Pending |