
Tarun Sinha
Examiner (ID: 10769, Phone: (571)270-3993 , Office: P/2856 )
| Most Active Art Unit | 2863 |
| Art Unit(s) | 2863, 2861, 2855, 2856 |
| Total Applications | 732 |
| Issued Applications | 531 |
| Pending Applications | 72 |
| Abandoned Applications | 142 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20695498
[patent_doc_number] => 20260126910
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-05-07
[patent_title] => SELF-MANAGED DRAM MODULES WITH BUILT-IN DATA COMPRESSION AND TIERED CACHING
[patent_app_type] => utility
[patent_app_number] => 18/937289
[patent_app_country] => US
[patent_app_date] => 2024-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937289
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/937289 | SELF-MANAGED DRAM MODULES WITH BUILT-IN DATA COMPRESSION AND TIERED CACHING | Nov 4, 2024 | Pending |
Array
(
[id] => 20745703
[patent_doc_number] => 12645615
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-02
[patent_title] => Ring buffer storage method and ring buffer storage system capable of minimizing extra overhead utilization
[patent_app_type] => utility
[patent_app_number] => 18/935642
[patent_app_country] => US
[patent_app_date] => 2024-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 4343
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935642
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/935642 | Ring buffer storage method and ring buffer storage system capable of minimizing extra overhead utilization | Nov 2, 2024 | Issued |
Array
(
[id] => 20680584
[patent_doc_number] => 20260119405
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-04-30
[patent_title] => INTERLEAVING CACHE LINE DATA TRANSFERS AND HANDLING MISSES OF SPECULATIVELY FETCHED DATA
[patent_app_type] => utility
[patent_app_number] => 18/928662
[patent_app_country] => US
[patent_app_date] => 2024-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5230
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928662
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/928662 | INTERLEAVING CACHE LINE DATA TRANSFERS AND HANDLING MISSES OF SPECULATIVELY FETCHED DATA | Oct 27, 2024 | Pending |
Array
(
[id] => 20380310
[patent_doc_number] => 20250362803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-27
[patent_title] => STORAGE DEVICE INCLUDING VOLATILE MEMORY AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/928200
[patent_app_country] => US
[patent_app_date] => 2024-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7995
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928200
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/928200 | STORAGE DEVICE INCLUDING VOLATILE MEMORY AND OPERATING METHOD THEREOF | Oct 27, 2024 | Pending |
Array
(
[id] => 20289948
[patent_doc_number] => 20250315191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-10-09
[patent_title] => READ STREAMING
[patent_app_type] => utility
[patent_app_number] => 18/925003
[patent_app_country] => US
[patent_app_date] => 2024-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14333
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18925003
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/925003 | READ STREAMING | Oct 22, 2024 | Pending |
Array
(
[id] => 19747754
[patent_doc_number] => 20250036319
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => MANAGING DATA COMPACTION FOR ZONES IN MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/918461
[patent_app_country] => US
[patent_app_date] => 2024-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11741
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18918461
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/918461 | MANAGING DATA COMPACTION FOR ZONES IN MEMORY DEVICES | Oct 16, 2024 | Pending |
Array
(
[id] => 20408677
[patent_doc_number] => 20250377786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-11
[patent_title] => CONTROLLERS, TEST SYSTEMS, MEMORY SYSTEMS, DATA PROCESSING METHODS AND DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/911022
[patent_app_country] => US
[patent_app_date] => 2024-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6725
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18911022
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/911022 | CONTROLLERS, TEST SYSTEMS, MEMORY SYSTEMS, DATA PROCESSING METHODS AND DEVICES | Oct 8, 2024 | Pending |
Array
(
[id] => 19992719
[patent_doc_number] => 20250130941
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-24
[patent_title] => PROCESSOR WITH HIGH-CAPACITY LAST-LEVEL CACHE
[patent_app_type] => utility
[patent_app_number] => 18/888496
[patent_app_country] => US
[patent_app_date] => 2024-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18888496
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/888496 | Processor with high-capacity last-level cache | Sep 17, 2024 | Issued |
Array
(
[id] => 20101940
[patent_doc_number] => 20250231876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-17
[patent_title] => STORAGE APPARATUS AND CONTROL METHOD FOR STORAGE APPARATUS
[patent_app_type] => utility
[patent_app_number] => 18/882315
[patent_app_country] => US
[patent_app_date] => 2024-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5560
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 433
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882315
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/882315 | Storage apparatus and control method for storage apparatus | Sep 10, 2024 | Issued |
Array
(
[id] => 20635628
[patent_doc_number] => 12596502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Electronic device and electronic device control method
[patent_app_type] => utility
[patent_app_number] => 18/882180
[patent_app_country] => US
[patent_app_date] => 2024-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 0
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882180
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/882180 | Electronic device and electronic device control method | Sep 10, 2024 | Issued |
Array
(
[id] => 19834066
[patent_doc_number] => 20250085852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-13
[patent_title] => FAST DECODING OF COMPRESSED DATA
[patent_app_type] => utility
[patent_app_number] => 18/830072
[patent_app_country] => US
[patent_app_date] => 2024-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4833
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830072
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/830072 | Fast decoding of compressed data | Sep 9, 2024 | Issued |
Array
(
[id] => 20689208
[patent_doc_number] => 12619357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-05
[patent_title] => Memory system controlling nonvolatile memory
[patent_app_type] => utility
[patent_app_number] => 18/791933
[patent_app_country] => US
[patent_app_date] => 2024-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 15551
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791933
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/791933 | Memory system controlling nonvolatile memory | Jul 31, 2024 | Issued |
Array
(
[id] => 19725892
[patent_doc_number] => 20250028643
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-23
[patent_title] => MEMORY POOLING BANDWIDTH MULTIPLIER USING FINAL LEVEL CACHE SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/781917
[patent_app_country] => US
[patent_app_date] => 2024-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 33084
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781917
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/781917 | MEMORY POOLING BANDWIDTH MULTIPLIER USING FINAL LEVEL CACHE SYSTEM | Jul 22, 2024 | Pending |
Array
(
[id] => 19558578
[patent_doc_number] => 20240370370
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => Dynamic Migration Of Point-Of-Coherency And Point-Of-Serialization In NUMA Coherent Interconnects
[patent_app_type] => utility
[patent_app_number] => 18/777045
[patent_app_country] => US
[patent_app_date] => 2024-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7889
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777045
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/777045 | Dynamic Migration Of Point-Of-Coherency And Point-Of-Serialization In NUMA Coherent Interconnects | Jul 17, 2024 | Pending |
Array
(
[id] => 19545126
[patent_doc_number] => 20240362162
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-31
[patent_title] => MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/768198
[patent_app_country] => US
[patent_app_date] => 2024-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14549
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768198
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/768198 | Memory system and method for controlling nonvolatile memory | Jul 9, 2024 | Issued |
Array
(
[id] => 20461053
[patent_doc_number] => 20260010481
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-08
[patent_title] => GAT BLOCK ALLOCATION
[patent_app_type] => utility
[patent_app_number] => 18/766012
[patent_app_country] => US
[patent_app_date] => 2024-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2375
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766012
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/766012 | GAT BLOCK ALLOCATION | Jul 7, 2024 | Pending |
Array
(
[id] => 19558580
[patent_doc_number] => 20240370372
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => METHODS AND APPARATUSES FOR DYNAMICALLY CHANGING DATA PRIORITY IN A CACHE
[patent_app_type] => utility
[patent_app_number] => 18/763009
[patent_app_country] => US
[patent_app_date] => 2024-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 41898
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763009
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/763009 | METHODS AND APPARATUSES FOR DYNAMICALLY CHANGING DATA PRIORITY IN A CACHE | Jul 2, 2024 | Pending |
Array
(
[id] => 19530097
[patent_doc_number] => 20240353999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => TEMPORAL METRIC DRIVEN MEDIA MANAGEMENT SCHEME
[patent_app_type] => utility
[patent_app_number] => 18/759614
[patent_app_country] => US
[patent_app_date] => 2024-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9414
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759614
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/759614 | Temporal metric driven media management scheme | Jun 27, 2024 | Issued |
Array
(
[id] => 19686108
[patent_doc_number] => 20250004653
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => DYNAMIC MEMORY RECONFIGURATION
[patent_app_type] => utility
[patent_app_number] => 18/756976
[patent_app_country] => US
[patent_app_date] => 2024-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5708
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756976
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/756976 | Dynamic memory reconfiguration | Jun 26, 2024 | Issued |
Array
(
[id] => 20717134
[patent_doc_number] => 12632385
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-19
[patent_title] => Coherent communication between a processor core and an accelerator
[patent_app_type] => utility
[patent_app_number] => 18/754079
[patent_app_country] => US
[patent_app_date] => 2024-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 11420
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754079
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/754079 | Coherent communication between a processor core and an accelerator | Jun 24, 2024 | Issued |