Search

Tat Chi Chio

Examiner (ID: 12943, Phone: (571)272-9563 , Office: P/2486 )

Most Active Art Unit
2486
Art Unit(s)
2112, 2609, 2486, 2621, 2481
Total Applications
962
Issued Applications
654
Pending Applications
94
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18959192 [patent_doc_number] => 20240047519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SHALLOW TRENCH ISOLATION STRUCTURE AND SEMICONDUCTOR DEVICE WITH THE SAME [patent_app_type] => utility [patent_app_number] => 18/380616 [patent_app_country] => US [patent_app_date] => 2023-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18380616 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/380616
Semiconductor device with shallow trench isolation having multi-stacked layers and method of forming the same Oct 15, 2023 Issued
Array ( [id] => 19733930 [patent_doc_number] => 12211932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Semiconductor device with improved breakdown voltage [patent_app_type] => utility [patent_app_number] => 18/484710 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7029 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/484710
Semiconductor device with improved breakdown voltage Oct 10, 2023 Issued
Array ( [id] => 18906123 [patent_doc_number] => 20240021608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE HAVING EMBEDDED PASSIVE DEVICE [patent_app_type] => utility [patent_app_number] => 18/478056 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/478056
SEMICONDUCTOR PACKAGE WITH REDISTRIBUTION SUBSTRATE HAVING EMBEDDED PASSIVE DEVICE Sep 28, 2023 Pending
Array ( [id] => 19130843 [patent_doc_number] => 20240136196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => METHOD FOR PREPARING A SURFACE FOR DIRECT-BONDING [patent_app_type] => utility [patent_app_number] => 18/475977 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475977 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475977
Method for preparing a surface for direct-bonding Sep 26, 2023 Issued
Array ( [id] => 19604907 [patent_doc_number] => 20240395787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => INTEGRATED CIRCUIT WITH STACKED INTERPOSER [patent_app_type] => utility [patent_app_number] => 18/476029 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3702 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18476029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/476029
INTEGRATED CIRCUIT WITH STACKED INTERPOSER Sep 26, 2023 Pending
Array ( [id] => 19130843 [patent_doc_number] => 20240136196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => METHOD FOR PREPARING A SURFACE FOR DIRECT-BONDING [patent_app_type] => utility [patent_app_number] => 18/475977 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3000 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475977 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475977
Method for preparing a surface for direct-bonding Sep 26, 2023 Issued
Array ( [id] => 19470577 [patent_doc_number] => 20240324247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DIE PAIR DEVICE PARTITIONING [patent_app_type] => utility [patent_app_number] => 18/474111 [patent_app_country] => US [patent_app_date] => 2023-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/474111
DIE PAIR DEVICE PARTITIONING Sep 24, 2023 Pending
Array ( [id] => 18883033 [patent_doc_number] => 20240006402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/466470 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18466470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/466470
SEMICONDUCTOR DEVICE Sep 12, 2023 Pending
Array ( [id] => 19575502 [patent_doc_number] => 20240379794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => 3DS FET AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/462613 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462613 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/462613
3DS FET AND METHOD OF MANUFACTURING THE SAME Sep 6, 2023 Pending
Array ( [id] => 18849045 [patent_doc_number] => 20230411449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/461679 [patent_app_country] => US [patent_app_date] => 2023-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18461679 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/461679
FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME Sep 5, 2023 Pending
Array ( [id] => 19421089 [patent_doc_number] => 20240297213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING [patent_app_type] => utility [patent_app_number] => 18/460171 [patent_app_country] => US [patent_app_date] => 2023-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460171 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/460171
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING Aug 31, 2023 Pending
Array ( [id] => 18821370 [patent_doc_number] => 20230395711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR MESAS BETWEEN ADJACENT GATE TRENCHES [patent_app_type] => utility [patent_app_number] => 18/453717 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453717
Semiconductor device with semiconductor mesas between adjacent gate trenches Aug 21, 2023 Issued
Array ( [id] => 19597131 [patent_doc_number] => 12154985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices [patent_app_type] => utility [patent_app_number] => 18/232640 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 8897 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232640 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232640
Moon-shaped bottom spacer for vertical transport field effect transistor (VTFET) devices Aug 9, 2023 Issued
Array ( [id] => 19437864 [patent_doc_number] => 20240306362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => INTERCONNECT STRUCTURES FOR INTEGRATION OF MEMORY CELLS AND LOGIC CELLS [patent_app_type] => utility [patent_app_number] => 18/446576 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446576 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446576
INTERCONNECT STRUCTURES FOR INTEGRATION OF MEMORY CELLS AND LOGIC CELLS Aug 8, 2023 Pending
Array ( [id] => 19116604 [patent_doc_number] => 20240128354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/231549 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/231549
SEMICONDUCTOR DEVICES Aug 7, 2023 Pending
Array ( [id] => 20443094 [patent_doc_number] => 12513940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Vertical transistors and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/230750 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 67 [patent_no_of_words] => 7032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230750
Vertical transistors and methods for forming the same Aug 6, 2023 Issued
Array ( [id] => 19086370 [patent_doc_number] => 20240113171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/365447 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365447
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Aug 3, 2023 Pending
Array ( [id] => 19494265 [patent_doc_number] => 12112988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Hybrid isolation regions having upper and lower portions with seams [patent_app_type] => utility [patent_app_number] => 18/361566 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7598 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361566 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361566
Hybrid isolation regions having upper and lower portions with seams Jul 27, 2023 Issued
Array ( [id] => 18774534 [patent_doc_number] => 20230369365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => LIGHT RECEIVING ELEMENT ARRAY AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/360021 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8246 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360021
LIGHT RECEIVING ELEMENT ARRAY AND MANUFACTURING METHOD THEREFOR Jul 26, 2023 Pending
Array ( [id] => 18774572 [patent_doc_number] => 20230369403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => Radiation Hardened High Voltage Superjunction MOSFET [patent_app_type] => utility [patent_app_number] => 18/358282 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358282
Radiation hardened high voltage superjunction MOSFET Jul 24, 2023 Issued
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