Search

Tat Chi Chio

Examiner (ID: 12943, Phone: (571)272-9563 , Office: P/2486 )

Most Active Art Unit
2486
Art Unit(s)
2112, 2609, 2486, 2621, 2481
Total Applications
962
Issued Applications
654
Pending Applications
94
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18296394 [patent_doc_number] => 20230106080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => UP-DIFFUSION SUPPRESSION IN A POWER MOSFET [patent_app_type] => utility [patent_app_number] => 18/063086 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063086 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063086
Up-diffusion suppression in a power MOSFET Dec 7, 2022 Issued
Array ( [id] => 18295092 [patent_doc_number] => 20230104778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/077790 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077790
High voltage edge termination structure for power semiconductor devices Dec 7, 2022 Issued
Array ( [id] => 18298982 [patent_doc_number] => 20230108668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/077670 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077670
High voltage edge termination structure for power semiconductor devices and manufacturing method thereof Dec 7, 2022 Issued
Array ( [id] => 18293618 [patent_doc_number] => 20230103304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => HIGH VOLTAGE EDGE TERMINATION STRUCTURE FOR POWER SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/077731 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18077731 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/077731
High voltage edge termination structure for power semiconductor devices and manufacturing method thereof Dec 7, 2022 Issued
Array ( [id] => 18298663 [patent_doc_number] => 20230108349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => VOLTAGE-SUSTAINING LAYER FOR SEMICONDUCTORS [patent_app_type] => utility [patent_app_number] => 18/063572 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063572
VOLTAGE-SUSTAINING LAYER FOR SEMICONDUCTORS Dec 7, 2022 Pending
Array ( [id] => 18600331 [patent_doc_number] => 20230275132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/062827 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062827 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062827
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Dec 6, 2022 Pending
Array ( [id] => 19494379 [patent_doc_number] => 12113103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Charge-balance power device, and process for manufacturing the charge-balance power device [patent_app_type] => utility [patent_app_number] => 18/062524 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 8294 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18062524 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/062524
Charge-balance power device, and process for manufacturing the charge-balance power device Dec 5, 2022 Issued
Array ( [id] => 18653354 [patent_doc_number] => 20230299194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/061673 [patent_app_country] => US [patent_app_date] => 2022-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5886 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061673 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061673
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Dec 4, 2022 Pending
Array ( [id] => 18271540 [patent_doc_number] => 20230092782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/060972 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18060972 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/060972
Manufacturing method of semiconductor device Dec 1, 2022 Issued
Array ( [id] => 19221561 [patent_doc_number] => 20240186265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => SHIELDED GATE TRENCH MOSFETS WITH HEXAGONAL DEEP TRENCH LAYOUTS AND MULTIPLE EPITAXIAL LAYERS [patent_app_type] => utility [patent_app_number] => 18/073964 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/073964
SHIELDED GATE TRENCH MOSFETS WITH HEXAGONAL DEEP TRENCH LAYOUTS AND MULTIPLE EPITAXIAL LAYERS Dec 1, 2022 Pending
Array ( [id] => 19101162 [patent_doc_number] => 20240120390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => TRENCH GATE TYPE IGBT [patent_app_type] => utility [patent_app_number] => 18/073388 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073388 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/073388
TRENCH GATE TYPE IGBT Nov 30, 2022 Pending
Array ( [id] => 18735798 [patent_doc_number] => 11804540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Vertical field effect transistor (VFET) structure with dielectric protection layer and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/071168 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6699 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071168 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/071168
Vertical field effect transistor (VFET) structure with dielectric protection layer and method of manufacturing the same Nov 28, 2022 Issued
Array ( [id] => 18424068 [patent_doc_number] => 20230178532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/985656 [patent_app_country] => US [patent_app_date] => 2022-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/985656
DISPLAY DEVICE Nov 10, 2022 Pending
Array ( [id] => 18362514 [patent_doc_number] => 20230144105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => IMAGE SENSOR INCLUDING A BURIED GATE [patent_app_type] => utility [patent_app_number] => 18/053744 [patent_app_country] => US [patent_app_date] => 2022-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/053744
IMAGE SENSOR INCLUDING A BURIED GATE Nov 7, 2022 Pending
Array ( [id] => 18490392 [patent_doc_number] => 20230217746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => LIGHT EMITTING DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/978012 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17978012 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/978012
LIGHT EMITTING DISPLAY APPARATUS Oct 30, 2022 Pending
Array ( [id] => 18473202 [patent_doc_number] => 20230207490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => SURFACE-MOUNT DEVICE WIRE BONDING IN SEMICONDUCTOR DEVICE ASSEMBLIES [patent_app_type] => utility [patent_app_number] => 17/976625 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/976625
SURFACE-MOUNT DEVICE WIRE BONDING IN SEMICONDUCTOR DEVICE ASSEMBLIES Oct 27, 2022 Pending
Array ( [id] => 19376833 [patent_doc_number] => 12068415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance [patent_app_type] => utility [patent_app_number] => 17/966817 [patent_app_country] => US [patent_app_date] => 2022-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 11330 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 414 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17966817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/966817
Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance Oct 14, 2022 Issued
Array ( [id] => 18227083 [patent_doc_number] => 20230066077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE WITH SPACER OF GRADUALLY CHANGED THICKNESS AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/046780 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046780 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046780
Semiconductor device with spacer of gradually changed thickness and manufacturing method thereof, and electronic device including the semiconductor device Oct 13, 2022 Issued
Array ( [id] => 18224999 [patent_doc_number] => 20230063993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR DEVICE WITH SPACER OF GRADUALLY CHANGED THICKNESS AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/046791 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046791
Semiconductor device with spacer of gradually changed thickness and manufacturing method thereof, and electronic device including the semiconductor device Oct 13, 2022 Issued
Array ( [id] => 18306950 [patent_doc_number] => 20230110850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => DISPLAY PANEL AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/045207 [patent_app_country] => US [patent_app_date] => 2022-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18045207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/045207
DISPLAY PANEL AND DISPLAY APPARATUS Oct 9, 2022 Pending
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