Search

Tat Chi Chio

Examiner (ID: 12943, Phone: (571)272-9563 , Office: P/2486 )

Most Active Art Unit
2486
Art Unit(s)
2112, 2609, 2486, 2621, 2481
Total Applications
962
Issued Applications
654
Pending Applications
94
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18440206 [patent_doc_number] => 20230187501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/937676 [patent_app_country] => US [patent_app_date] => 2022-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17937676 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/937676
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Oct 2, 2022 Pending
Array ( [id] => 19086220 [patent_doc_number] => 20240113021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH SHARED BACKSIDE POWER SUPPLY [patent_app_type] => utility [patent_app_number] => 17/936393 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936393 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936393
VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH SHARED BACKSIDE POWER SUPPLY Sep 28, 2022 Pending
Array ( [id] => 18743420 [patent_doc_number] => 20230352408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING BACKSIDE POWER RAIL AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/936106 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936106 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936106
Integrated circuit devices including backside power rail and methods of forming the same Sep 27, 2022 Issued
Array ( [id] => 20189835 [patent_doc_number] => 12400960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Vertical-transport field-effect transistor with backside gate contact [patent_app_type] => utility [patent_app_number] => 17/936202 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936202
Vertical-transport field-effect transistor with backside gate contact Sep 27, 2022 Issued
Array ( [id] => 18141672 [patent_doc_number] => 20230015515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => INSULATED GATE BIPOLAR TRANSISTOR AND PREPARATION METHOD THEREOF, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/953822 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953822
INSULATED GATE BIPOLAR TRANSISTOR AND PREPARATION METHOD THEREOF, AND ELECTRONIC DEVICE Sep 26, 2022 Pending
Array ( [id] => 20267006 [patent_doc_number] => 12438004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Method for forming semiconductor device that includes flash memory [patent_app_type] => utility [patent_app_number] => 17/951494 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17951494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/951494
Method for forming semiconductor device that includes flash memory Sep 22, 2022 Issued
Array ( [id] => 20191161 [patent_doc_number] => 12402299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Semiconductor memory device with nanowire structure and forming method thereof [patent_app_type] => utility [patent_app_number] => 17/933142 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933142 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933142
Semiconductor memory device with nanowire structure and forming method thereof Sep 18, 2022 Issued
Array ( [id] => 19038219 [patent_doc_number] => 20240088034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => GAA DEVICE WITH THE SUBSTRATE INCLUDING EMBEDDED INSULATING STRUCTURE BETWEEN BSPDN AND CHANNELS [patent_app_type] => utility [patent_app_number] => 17/930739 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17930739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/930739
GAA DEVICE WITH THE SUBSTRATE INCLUDING EMBEDDED INSULATING STRUCTURE BETWEEN BSPDN AND CHANNELS Sep 8, 2022 Pending
Array ( [id] => 18661495 [patent_doc_number] => 20230307509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/939025 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939025
SEMICONDUCTOR DEVICE Sep 6, 2022 Pending
Array ( [id] => 19023145 [patent_doc_number] => 20240079316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => LOCAL ENLARGED VIA-TO-BACKSIDE POWER RAIL [patent_app_type] => utility [patent_app_number] => 17/903644 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/903644
Local enlarged via-to-backside power rail Sep 5, 2022 Issued
Array ( [id] => 18097738 [patent_doc_number] => 20220416079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A POWER MOSFET AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/901416 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901416 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901416
Manafacturing method for power MOSFET semiconductor device with improved breakdown voltage Aug 31, 2022 Issued
Array ( [id] => 19008093 [patent_doc_number] => 20240072164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => VTFET WITH CONTROLLED FIN HEIGHT [patent_app_type] => utility [patent_app_number] => 17/823799 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823799
VTFET with controlled fin height Aug 30, 2022 Issued
Array ( [id] => 20082608 [patent_doc_number] => 12356709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Vertical field-effect transistor with isolation pillars [patent_app_type] => utility [patent_app_number] => 17/895299 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 3194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895299
Vertical field-effect transistor with isolation pillars Aug 24, 2022 Issued
Array ( [id] => 18258489 [patent_doc_number] => 20230085529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/892177 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892177 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892177
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD Aug 21, 2022 Pending
Array ( [id] => 18615953 [patent_doc_number] => 20230282692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/889945 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889945
Semiconductor device having control electrodes in termination region Aug 16, 2022 Issued
Array ( [id] => 18310418 [patent_doc_number] => 20230114318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/886496 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886496 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886496
Display device Aug 11, 2022 Issued
Array ( [id] => 18348808 [patent_doc_number] => 20230136919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => IMAGE SENSOR AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/886578 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886578
IMAGE SENSOR AND METHOD OF FABRICATING THE SAME Aug 11, 2022 Pending
Array ( [id] => 18211922 [patent_doc_number] => 20230058186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => ULTRA-SHALLOW DOPANT AND OHMIC CONTACT REGIONS BY SOLID STATE DIFFUSION [patent_app_type] => utility [patent_app_number] => 17/884090 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884090 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884090
Ultra-shallow dopant and ohmic contact regions by solid state diffusion Aug 8, 2022 Issued
Array ( [id] => 18024549 [patent_doc_number] => 20220376048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => Semiconductor Device Including Insulated Gate Bipolar Transistor [patent_app_type] => utility [patent_app_number] => 17/881926 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881926 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881926
Semiconductor device including insulated gate bipolar transistor Aug 4, 2022 Issued
Array ( [id] => 18943621 [patent_doc_number] => 20240038760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => INTEGRATED CIRCUIT CELL WITH DUAL ROW, BACK-TO-BACK, TRANSISTOR BODY TIES [patent_app_type] => utility [patent_app_number] => 17/878825 [patent_app_country] => US [patent_app_date] => 2022-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878825 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/878825
INTEGRATED CIRCUIT CELL WITH DUAL ROW, BACK-TO-BACK, TRANSISTOR BODY TIES Jul 31, 2022 Pending
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