Search

Tat Chi Chio

Examiner (ID: 12943, Phone: (571)272-9563 , Office: P/2486 )

Most Active Art Unit
2486
Art Unit(s)
2112, 2609, 2486, 2621, 2481
Total Applications
962
Issued Applications
654
Pending Applications
94
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18999289 [patent_doc_number] => 11916145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Independent control of stacked semiconductor device [patent_app_type] => utility [patent_app_number] => 17/815396 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 9671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815396
Independent control of stacked semiconductor device Jul 26, 2022 Issued
Array ( [id] => 19244630 [patent_doc_number] => 12015085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Method of manufacturing a semiconductor device including etching polysilicon [patent_app_type] => utility [patent_app_number] => 17/874281 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 9174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874281
Method of manufacturing a semiconductor device including etching polysilicon Jul 25, 2022 Issued
Array ( [id] => 20347543 [patent_doc_number] => 12471281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Methods used in forming memory arrays having strings of memory cells [patent_app_type] => utility [patent_app_number] => 17/869586 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 35 [patent_no_of_words] => 2159 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869586 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869586
Methods used in forming memory arrays having strings of memory cells Jul 19, 2022 Issued
Array ( [id] => 18804342 [patent_doc_number] => 11837505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Formation of hybrid isolation regions through recess and re-deposition [patent_app_type] => utility [patent_app_number] => 17/813862 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 7570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813862
Formation of hybrid isolation regions through recess and re-deposition Jul 19, 2022 Issued
Array ( [id] => 19597073 [patent_doc_number] => 12154927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/866603 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866603
Semiconductor structure Jul 17, 2022 Issued
Array ( [id] => 19314573 [patent_doc_number] => 12040400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Method for forming semiconductor device structure with nanostructure [patent_app_type] => utility [patent_app_number] => 17/866803 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 9682 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866803
Method for forming semiconductor device structure with nanostructure Jul 17, 2022 Issued
Array ( [id] => 17986276 [patent_doc_number] => 20220352313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 17/866986 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866986 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866986
Semiconductor devices having gate structures with slanted sidewalls Jul 17, 2022 Issued
Array ( [id] => 18548397 [patent_doc_number] => 11721759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Method for forming gate metal structure having portions with different heights [patent_app_type] => utility [patent_app_number] => 17/811588 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5009 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17811588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/811588
Method for forming gate metal structure having portions with different heights Jul 10, 2022 Issued
Array ( [id] => 18882989 [patent_doc_number] => 20240006358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SUBSTRATE TRENCH FOR IMPROVED HYBRID BONDING [patent_app_type] => utility [patent_app_number] => 17/854813 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10322 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854813
SUBSTRATE TRENCH FOR IMPROVED HYBRID BONDING Jun 29, 2022 Pending
Array ( [id] => 18183615 [patent_doc_number] => 20230044345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => LAYOUT STRUCTURE OF FLEXIBLE CIRCUIT BOARD [patent_app_type] => utility [patent_app_number] => 17/848481 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848481
LAYOUT STRUCTURE OF FLEXIBLE CIRCUIT BOARD Jun 23, 2022 Abandoned
Array ( [id] => 18848873 [patent_doc_number] => 20230411277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => EMBEDDED CAPACITORS WITH SHARED ELECTRODES [patent_app_type] => utility [patent_app_number] => 17/842972 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842972
EMBEDDED CAPACITORS WITH SHARED ELECTRODES Jun 16, 2022 Pending
Array ( [id] => 18849119 [patent_doc_number] => 20230411523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => VERTICAL FIELD EFFECT TRANSISTOR WITH STRAINED CHANNEL [patent_app_type] => utility [patent_app_number] => 17/807011 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807011 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/807011
VERTICAL FIELD EFFECT TRANSISTOR WITH STRAINED CHANNEL Jun 14, 2022 Pending
Array ( [id] => 17900733 [patent_doc_number] => 20220310395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/839682 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839682 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/839682
Semiconductor structure and method of manufacturing the same Jun 13, 2022 Issued
Array ( [id] => 19050660 [patent_doc_number] => 20240092629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => INTEGRATED MEMS ELECTROSTATIC MICRO-SPEAKER DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/838780 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17838780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/838780
Integrated MEMS electrostatic micro-speaker device and method Jun 12, 2022 Issued
Array ( [id] => 18126740 [patent_doc_number] => 20230012361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => POWER SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/837547 [patent_app_country] => US [patent_app_date] => 2022-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17837547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/837547
POWER SEMICONDUCTOR DEVICE Jun 9, 2022 Pending
Array ( [id] => 19705123 [patent_doc_number] => 12199171 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-14 [patent_title] => Vertical tunneling field-effect transistor with enhanced current confinement [patent_app_type] => utility [patent_app_number] => 17/830874 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5379 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17830874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/830874
Vertical tunneling field-effect transistor with enhanced current confinement Jun 1, 2022 Issued
Array ( [id] => 18113224 [patent_doc_number] => 20230006104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => INORGANIC LIGHT EMITTING DIODE, DISPLAY MODULE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/826441 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17826441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/826441
INORGANIC LIGHT EMITTING DIODE, DISPLAY MODULE AND MANUFACTURING METHOD THEREOF May 26, 2022 Pending
Array ( [id] => 18623943 [patent_doc_number] => 11757001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Radiation hardened high voltage superjunction MOSFET [patent_app_type] => utility [patent_app_number] => 17/804491 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6457 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17804491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/804491
Radiation hardened high voltage superjunction MOSFET May 26, 2022 Issued
Array ( [id] => 19590074 [patent_doc_number] => 20240387631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => NANOWIRE, FABRICATION METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/273730 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18273730 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/273730
NANOWIRE, FABRICATION METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE AND ELECTRONIC DEVICE May 23, 2022 Pending
Array ( [id] => 18812858 [patent_doc_number] => 20230387195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => FIELD TERMINATION STRUCTURE FOR MONOLITHICALLY INTEGRATED POWER SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/751909 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751909 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751909
FIELD TERMINATION STRUCTURE FOR MONOLITHICALLY INTEGRATED POWER SEMICONDUCTOR DEVICES May 23, 2022 Pending
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