Search

Tat Chi Chio

Examiner (ID: 12943, Phone: (571)272-9563 , Office: P/2486 )

Most Active Art Unit
2486
Art Unit(s)
2112, 2609, 2486, 2621, 2481
Total Applications
962
Issued Applications
654
Pending Applications
94
Abandoned Applications
239

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17811075 [patent_doc_number] => 20220262910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => CONTACT STRUCTURE FOR TRANSISTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/738049 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738049
Contact structure for transistor devices May 5, 2022 Issued
Array ( [id] => 18500544 [patent_doc_number] => 20230223338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => EQUALIZATION CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF, SENSE AMPLIFICATION CIRCUIT STRUCTURE AND MEMORY CIRCUIT STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/661548 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5828 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661548
Equalization circuit structure and manufacturing method thereof, sense amplification circuit structure and memory circuit structure Apr 28, 2022 Issued
Array ( [id] => 17795655 [patent_doc_number] => 20220254747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/729728 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729728
Semiconductor package and method for manufacturing the same Apr 25, 2022 Issued
Array ( [id] => 17780405 [patent_doc_number] => 20220246755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => METHOD OF MANUFACTURING MOSFET [patent_app_type] => utility [patent_app_number] => 17/726536 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726536 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726536
Method of manufacturing MOSFET having a semiconductor base substrate with a super junction structure Apr 21, 2022 Issued
Array ( [id] => 17780372 [patent_doc_number] => 20220246722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 17/727091 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727091 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/727091
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Apr 21, 2022 Abandoned
Array ( [id] => 18729400 [patent_doc_number] => 20230343696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MAKING [patent_app_type] => utility [patent_app_number] => 17/725015 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25776 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725015 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725015
Semiconductor device including first and second transistor channels Apr 19, 2022 Issued
Array ( [id] => 18579055 [patent_doc_number] => 11735595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Thin film tunnel field effect transistors having relatively increased width [patent_app_type] => utility [patent_app_number] => 17/721236 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 11988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721236
Thin film tunnel field effect transistors having relatively increased width Apr 13, 2022 Issued
Array ( [id] => 17764774 [patent_doc_number] => 20220238387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Gate Profile Control Through Sidewall Protection During Etching [patent_app_type] => utility [patent_app_number] => 17/658697 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/658697
Gate Profile Control Through Sidewall Protection During Etching Apr 10, 2022 Pending
Array ( [id] => 17752920 [patent_doc_number] => 20220231125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => Power Semiconductor Device Having a Control Cell for Controlling a Load Current [patent_app_type] => utility [patent_app_number] => 17/716555 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716555
Power semiconductor device having a control cell for controlling a load current Apr 7, 2022 Issued
Array ( [id] => 18680009 [patent_doc_number] => 20230317667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SEMICONDUCTOR DEVICE WITH METAL SILICIDE LAYER [patent_app_type] => utility [patent_app_number] => 17/712750 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712750 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712750
Semiconductor device with metal silicide layer Apr 3, 2022 Issued
Array ( [id] => 17738227 [patent_doc_number] => 20220223689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => Methods Of Forming Epitaxial Source/Drain Features In Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/705540 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705540
Methods of forming epitaxial source/drain features in semiconductor devices Mar 27, 2022 Issued
Array ( [id] => 17723520 [patent_doc_number] => 20220216242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => SHIFT REGISTER AND DISPLAY DEVICE AND DRIVING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/704109 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704109
SHIFT REGISTER AND DISPLAY DEVICE AND DRIVING METHOD THEREOF Mar 24, 2022 Abandoned
Array ( [id] => 19679488 [patent_doc_number] => 12191361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Transistor structure with multi-layer field plate and related method [patent_app_type] => utility [patent_app_number] => 17/656277 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656277 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656277
Transistor structure with multi-layer field plate and related method Mar 23, 2022 Issued
Array ( [id] => 17723516 [patent_doc_number] => 20220216238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => Semiconductor Circuit with Metal Structure and Manufacturing Method [patent_app_type] => utility [patent_app_number] => 17/700853 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17700853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/700853
Semiconductor circuit with metal structure and manufacturing method Mar 21, 2022 Issued
Array ( [id] => 19221673 [patent_doc_number] => 20240186377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => POWER SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/550219 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18550219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/550219
POWER SEMICONDUCTOR DEVICE Mar 21, 2022 Pending
Array ( [id] => 20162973 [patent_doc_number] => 12389630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Vertical channel transistor including a graphene insertion layer beweeen a source/drain electrode and a channel pattern [patent_app_type] => utility [patent_app_number] => 17/697400 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2121 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697400 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/697400
Vertical channel transistor including a graphene insertion layer beweeen a source/drain electrode and a channel pattern Mar 16, 2022 Issued
Array ( [id] => 17901176 [patent_doc_number] => 20220310838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A TRENCH STRUCURE [patent_app_type] => utility [patent_app_number] => 17/695207 [patent_app_country] => US [patent_app_date] => 2022-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17695207 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/695207
Semiconductor device including a trench structure having a trench dielectric structure with a gap Mar 14, 2022 Issued
Array ( [id] => 18196255 [patent_doc_number] => 20230049774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING AN ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/685973 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685973 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685973
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING AN ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT Mar 2, 2022 Pending
Array ( [id] => 19928255 [patent_doc_number] => 12302566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Semiconductor memory device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/685896 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 38 [patent_no_of_words] => 8155 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685896 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685896
Semiconductor memory device and method for manufacturing the same Mar 2, 2022 Issued
Array ( [id] => 17855524 [patent_doc_number] => 20220285567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => METHOD FOR THROUGH-HOLE PLATING [patent_app_type] => utility [patent_app_number] => 17/685074 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685074
METHOD FOR THROUGH-HOLE PLATING Mar 1, 2022 Pending
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