
Tat Chi Chio
Examiner (ID: 14792, Phone: (571)272-9563 , Office: P/2486 )
| Most Active Art Unit | 2486 |
| Art Unit(s) | 2621, 2481, 2609, 2486, 2112 |
| Total Applications | 970 |
| Issued Applications | 657 |
| Pending Applications | 95 |
| Abandoned Applications | 239 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6866372
[patent_doc_number] => 20030191898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'Replacement data error detector'
[patent_app_type] => new
[patent_app_number] => 10/411589
[patent_app_country] => US
[patent_app_date] => 2003-04-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0191/20030191898.pdf
[firstpage_image] =>[orig_patent_app_number] => 10411589
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/411589 | Replacement data error detector | Apr 9, 2003 | Issued |
Array
(
[id] => 7360712
[patent_doc_number] => 20040049656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-11
[patent_title] => 'Processor and instruction execution method with reduced address information'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/395849 | Processor and instruction execution method with reduced address information | Mar 24, 2003 | Issued |
Array
(
[id] => 7246436
[patent_doc_number] => 20040158669
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[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Architecture for a serial ATA bus based flash memory apparatus'
[patent_app_type] => new
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[patent_app_date] => 2003-03-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/397092 | Architecture for a serial ATA bus based flash memory apparatus | Mar 23, 2003 | Abandoned |
Array
(
[id] => 947626
[patent_doc_number] => 06965961
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-11-15
[patent_title] => 'Queue-based spin lock with timeout'
[patent_app_type] => utility
[patent_app_number] => 10/377024
[patent_app_country] => US
[patent_app_date] => 2003-03-03
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[firstpage_image] =>[orig_patent_app_number] => 10377024
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/377024 | Queue-based spin lock with timeout | Mar 2, 2003 | Issued |
Array
(
[id] => 731100
[patent_doc_number] => 07047374
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-16
[patent_title] => 'Memory read/write reordering'
[patent_app_type] => utility
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[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/358745 | Memory read/write reordering | Feb 4, 2003 | Issued |
Array
(
[id] => 7391492
[patent_doc_number] => 20040022094
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[patent_kind] => A1
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[patent_title] => 'Cache usage for concurrent multiple streams'
[patent_app_type] => new
[patent_app_number] => 10/358618
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/358618 | Cache usage for concurrent multiple streams | Feb 4, 2003 | Abandoned |
Array
(
[id] => 7621223
[patent_doc_number] => 06978278
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[patent_issue_date] => 2005-12-20
[patent_title] => 'System and method for heterogeneous caching'
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[pdf_file] => patents/06/978/06978278.pdf
[firstpage_image] =>[orig_patent_app_number] => 10340067
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/340067 | System and method for heterogeneous caching | Jan 9, 2003 | Issued |
Array
(
[id] => 761530
[patent_doc_number] => 07020684
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[patent_kind] => B2
[patent_issue_date] => 2006-03-28
[patent_title] => 'System and method for optimistic caching'
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[pdf_file] => patents/07/020/07020684.pdf
[firstpage_image] =>[orig_patent_app_number] => 10340023
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/340023 | System and method for optimistic caching | Jan 9, 2003 | Issued |
Array
(
[id] => 971398
[patent_doc_number] => 06941438
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[patent_kind] => B2
[patent_issue_date] => 2005-09-06
[patent_title] => 'Memory interleaving'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/340220 | Memory interleaving | Jan 9, 2003 | Issued |
Array
(
[id] => 7621157
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[patent_title] => 'Shift register control of a circular elasticity buffer'
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[firstpage_image] =>[orig_patent_app_number] => 10323104
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/323104 | Shift register control of a circular elasticity buffer | Dec 17, 2002 | Issued |
Array
(
[id] => 933366
[patent_doc_number] => 06981120
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[patent_kind] => B1
[patent_issue_date] => 2005-12-27
[patent_title] => 'Method and apparatus for virtual memory segmentation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/287868 | Method and apparatus for virtual memory segmentation | Nov 3, 2002 | Issued |
Array
(
[id] => 736037
[patent_doc_number] => 07043599
[patent_country] => US
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[patent_title] => 'Dynamic memory supporting simultaneous refresh and data-access transactions'
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Array
(
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Array
(
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[patent_title] => 'Virtual mode virtual memory manager method and apparatus'
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232253 | Method and apparatus for non-volatile display of information for an electronic device | Aug 28, 2002 | Issued |
Array
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232430 | Multi-bank memory accesses using posted writes | Aug 27, 2002 | Issued |