Search

Tatiana L. Nobrega

Examiner (ID: 12123, Phone: (571)270-7228 , Office: P/3776 )

Most Active Art Unit
3776
Art Unit(s)
3772, 3732, 3799, 3776
Total Applications
676
Issued Applications
216
Pending Applications
72
Abandoned Applications
395

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 282357 [patent_doc_number] => 07554358 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-30 [patent_title] => 'Programmable logic devices with user non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/397985 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5536 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554358.pdf [firstpage_image] =>[orig_patent_app_number] => 11397985 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397985
Programmable logic devices with user non-volatile memory Apr 4, 2006 Issued
Array ( [id] => 580850 [patent_doc_number] => 07459931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-02 [patent_title] => 'Programmable logic devices with transparent field reconfiguration' [patent_app_type] => utility [patent_app_number] => 11/398437 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7350 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459931.pdf [firstpage_image] =>[orig_patent_app_number] => 11398437 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/398437
Programmable logic devices with transparent field reconfiguration Apr 4, 2006 Issued
Array ( [id] => 405135 [patent_doc_number] => 07288969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-30 [patent_title] => 'Zero clock delay metastability filtering circuit' [patent_app_type] => utility [patent_app_number] => 11/397570 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3483 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288969.pdf [firstpage_image] =>[orig_patent_app_number] => 11397570 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397570
Zero clock delay metastability filtering circuit Apr 4, 2006 Issued
Array ( [id] => 873760 [patent_doc_number] => 07362136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Dual voltage single gate oxide I/O circuit with high voltage stress tolerance' [patent_app_type] => utility [patent_app_number] => 11/397213 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3614 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362136.pdf [firstpage_image] =>[orig_patent_app_number] => 11397213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397213
Dual voltage single gate oxide I/O circuit with high voltage stress tolerance Apr 3, 2006 Issued
Array ( [id] => 282359 [patent_doc_number] => 07554360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-30 [patent_title] => 'High speed level shifter circuit in advanced CMOS technology' [patent_app_type] => utility [patent_app_number] => 11/398387 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4543 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/554/07554360.pdf [firstpage_image] =>[orig_patent_app_number] => 11398387 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/398387
High speed level shifter circuit in advanced CMOS technology Apr 3, 2006 Issued
Array ( [id] => 186275 [patent_doc_number] => 07646211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Circuit and apparatus for reducing interference of digital signals' [patent_app_type] => utility [patent_app_number] => 11/397920 [patent_app_country] => US [patent_app_date] => 2006-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 4259 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646211.pdf [firstpage_image] =>[orig_patent_app_number] => 11397920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397920
Circuit and apparatus for reducing interference of digital signals Apr 2, 2006 Issued
Array ( [id] => 304114 [patent_doc_number] => 07535255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Logic integrated circuit having dynamic substitution function, information processing apparatus using the same, and dynamic substitution method of logic integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/277625 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6034 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535255.pdf [firstpage_image] =>[orig_patent_app_number] => 11277625 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/277625
Logic integrated circuit having dynamic substitution function, information processing apparatus using the same, and dynamic substitution method of logic integrated circuit Mar 27, 2006 Issued
Array ( [id] => 5698007 [patent_doc_number] => 20060214691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Output buffer circuit' [patent_app_type] => utility [patent_app_number] => 11/390134 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2597 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214691.pdf [firstpage_image] =>[orig_patent_app_number] => 11390134 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/390134
Output buffer circuit Mar 27, 2006 Issued
Array ( [id] => 319250 [patent_doc_number] => 07521963 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-21 [patent_title] => 'System and method for providing a low standby power interface for a low voltage I2C compatible bus' [patent_app_type] => utility [patent_app_number] => 11/390014 [patent_app_country] => US [patent_app_date] => 2006-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4443 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/521/07521963.pdf [firstpage_image] =>[orig_patent_app_number] => 11390014 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/390014
System and method for providing a low standby power interface for a low voltage I2C compatible bus Mar 26, 2006 Issued
Array ( [id] => 861724 [patent_doc_number] => 07372298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Chip with adjustable pinout function and method thereof' [patent_app_type] => utility [patent_app_number] => 11/277361 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372298.pdf [firstpage_image] =>[orig_patent_app_number] => 11277361 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/277361
Chip with adjustable pinout function and method thereof Mar 23, 2006 Issued
Array ( [id] => 390773 [patent_doc_number] => 07301369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Programmable gate array apparatus and method for switching circuits' [patent_app_type] => utility [patent_app_number] => 11/387872 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10969 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301369.pdf [firstpage_image] =>[orig_patent_app_number] => 11387872 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/387872
Programmable gate array apparatus and method for switching circuits Mar 23, 2006 Issued
Array ( [id] => 873756 [patent_doc_number] => 07362134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-22 [patent_title] => 'Circuit and method for latch bypass' [patent_app_type] => utility [patent_app_number] => 11/388921 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/362/07362134.pdf [firstpage_image] =>[orig_patent_app_number] => 11388921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/388921
Circuit and method for latch bypass Mar 23, 2006 Issued
Array ( [id] => 143066 [patent_doc_number] => 07688107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Shift register, display device, and electronic device' [patent_app_type] => utility [patent_app_number] => 11/387782 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 10677 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/688/07688107.pdf [firstpage_image] =>[orig_patent_app_number] => 11387782 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/387782
Shift register, display device, and electronic device Mar 23, 2006 Issued
Array ( [id] => 590522 [patent_doc_number] => 07443203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Impedance adjustment circuit and integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/386813 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7902 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/443/07443203.pdf [firstpage_image] =>[orig_patent_app_number] => 11386813 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/386813
Impedance adjustment circuit and integrated circuit device Mar 22, 2006 Issued
Array ( [id] => 565671 [patent_doc_number] => 07471110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-30 [patent_title] => 'Current mode interface for off-chip high speed communication' [patent_app_type] => utility [patent_app_number] => 11/389332 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1737 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/471/07471110.pdf [firstpage_image] =>[orig_patent_app_number] => 11389332 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/389332
Current mode interface for off-chip high speed communication Mar 22, 2006 Issued
Array ( [id] => 901259 [patent_doc_number] => 07339396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Method and apparatus for ameliorating the effects of noise generated by a bus interface' [patent_app_type] => utility [patent_app_number] => 11/387411 [patent_app_country] => US [patent_app_date] => 2006-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2924 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/339/07339396.pdf [firstpage_image] =>[orig_patent_app_number] => 11387411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/387411
Method and apparatus for ameliorating the effects of noise generated by a bus interface Mar 22, 2006 Issued
Array ( [id] => 908628 [patent_doc_number] => 07332929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-19 [patent_title] => 'Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers' [patent_app_type] => utility [patent_app_number] => 11/308048 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332929.pdf [firstpage_image] =>[orig_patent_app_number] => 11308048 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308048
Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers Mar 2, 2006 Issued
Array ( [id] => 5681301 [patent_doc_number] => 20060197568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Slew rate calibrating circuit and slew rate calibrating method' [patent_app_type] => utility [patent_app_number] => 11/362819 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12579 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20060197568.pdf [firstpage_image] =>[orig_patent_app_number] => 11362819 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/362819
Slew rate calibrating circuit and slew rate calibrating method Feb 27, 2006 Issued
Array ( [id] => 5698006 [patent_doc_number] => 20060214690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Current drive circuit and method of boosting current using the same' [patent_app_type] => utility [patent_app_number] => 11/363338 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8570 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214690.pdf [firstpage_image] =>[orig_patent_app_number] => 11363338 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/363338
Current drive circuit and method of boosting current using the same Feb 26, 2006 Issued
Array ( [id] => 5099185 [patent_doc_number] => 20070182445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Efficient configuration of daisy-chained programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/346817 [patent_app_country] => US [patent_app_date] => 2006-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20070182445.pdf [firstpage_image] =>[orig_patent_app_number] => 11346817 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/346817
Efficient configuration of daisy-chained programmable logic devices Feb 2, 2006 Issued
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