Search

Taylor L. Morris

Examiner (ID: 13582, Phone: (571)272-6367 , Office: P/3631 )

Most Active Art Unit
3631
Art Unit(s)
3631
Total Applications
766
Issued Applications
408
Pending Applications
93
Abandoned Applications
282

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15128969 [patent_doc_number] => 10477911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Article of footwear and charging system [patent_app_type] => utility [patent_app_number] => 15/365047 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 13981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365047 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365047
Article of footwear and charging system Nov 29, 2016 Issued
Array ( [id] => 11459475 [patent_doc_number] => 20170053381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'INTERLACED BI-SENSOR SUPER-RESOLUTION ENHANCEMENT' [patent_app_type] => utility [patent_app_number] => 15/341547 [patent_app_country] => US [patent_app_date] => 2016-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3791 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15341547 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/341547
INTERLACED BI-SENSOR SUPER-RESOLUTION ENHANCEMENT Nov 1, 2016 Abandoned
Array ( [id] => 11494873 [patent_doc_number] => 20170069058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'INTERLACED BI-SENSOR SUPER-RESOLUTION ENHANCEMENT' [patent_app_type] => utility [patent_app_number] => 15/341536 [patent_app_country] => US [patent_app_date] => 2016-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3792 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15341536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/341536
Interlaced bi-sensor super-resolution enhancement Nov 1, 2016 Issued
Array ( [id] => 11494581 [patent_doc_number] => 20170068766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'INTERLACED BI-SENSOR SUPER-RESOLUTION ENHANCEMENT' [patent_app_type] => utility [patent_app_number] => 15/341522 [patent_app_country] => US [patent_app_date] => 2016-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3792 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15341522 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/341522
Interlaced bi-sensor super-resolution enhancement Nov 1, 2016 Issued
Array ( [id] => 12026040 [patent_doc_number] => 20170316138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'Method and System for Integrated Circuit Design With On-Chip Variation and Spatial Correlation' [patent_app_type] => utility [patent_app_number] => 15/335091 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7589 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335091 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/335091
Method and system for integrated circuit design with on-chip variation and spatial correlation Oct 25, 2016 Issued
Array ( [id] => 11917547 [patent_doc_number] => 09785735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => 'Parallel incremental global routing' [patent_app_type] => utility [patent_app_number] => 15/290279 [patent_app_country] => US [patent_app_date] => 2016-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290279 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/290279
Parallel incremental global routing Oct 10, 2016 Issued
Array ( [id] => 11882890 [patent_doc_number] => 09754064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Integrated circuit design method' [patent_app_type] => utility [patent_app_number] => 15/286357 [patent_app_country] => US [patent_app_date] => 2016-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5080 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15286357 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/286357
Integrated circuit design method Oct 4, 2016 Issued
Array ( [id] => 14177461 [patent_doc_number] => 10262751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Multi-dimensional optimization of electrical parameters for memory training [patent_app_type] => utility [patent_app_number] => 15/280320 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 16326 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280320 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/280320
Multi-dimensional optimization of electrical parameters for memory training Sep 28, 2016 Issued
Array ( [id] => 13017751 [patent_doc_number] => 10031990 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-24 [patent_title] => System, method, and computer program product for analyzing X-propagation failures in formal verification [patent_app_type] => utility [patent_app_number] => 15/278441 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4996 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278441 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278441
System, method, and computer program product for analyzing X-propagation failures in formal verification Sep 27, 2016 Issued
Array ( [id] => 11531381 [patent_doc_number] => 20170091360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'WAVEFORM BASED RECONSTRUCTION FOR EMULATION' [patent_app_type] => utility [patent_app_number] => 15/278659 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278659
Waveform based reconstruction for emulation Sep 27, 2016 Issued
Array ( [id] => 14490105 [patent_doc_number] => 10331843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-25 [patent_title] => System and method for visualization and analysis of a chip view including multiple circuit design revisions [patent_app_type] => utility [patent_app_number] => 15/277406 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277406 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277406
System and method for visualization and analysis of a chip view including multiple circuit design revisions Sep 26, 2016 Issued
Array ( [id] => 14092467 [patent_doc_number] => 10242141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Reset sequencing for reducing noise on a power distribution network [patent_app_type] => utility [patent_app_number] => 15/277414 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5808 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277414 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277414
Reset sequencing for reducing noise on a power distribution network Sep 26, 2016 Issued
Array ( [id] => 13797765 [patent_doc_number] => 20190012421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => PCB STENCIL MANUFACTURING METHOD AND SYSTEM [patent_app_type] => utility [patent_app_number] => 16/066496 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16066496 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/066496
PCB stencil manufacturing method and system Sep 22, 2016 Issued
Array ( [id] => 15198565 [patent_doc_number] => 10496779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Generating root cause candidates for yield analysis [patent_app_type] => utility [patent_app_number] => 15/263014 [patent_app_country] => US [patent_app_date] => 2016-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15263014 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/263014
Generating root cause candidates for yield analysis Sep 11, 2016 Issued
Array ( [id] => 11338758 [patent_doc_number] => 20160364513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'VARIABLE ACCURACY PARAMETER MODELING IN STATISTICAL TIMING' [patent_app_type] => utility [patent_app_number] => 15/235168 [patent_app_country] => US [patent_app_date] => 2016-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15235168 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/235168
Variable accuracy parameter modeling in statistical timing Aug 11, 2016 Issued
Array ( [id] => 13258109 [patent_doc_number] => 10141755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Multi-functional portable power charger [patent_app_type] => utility [patent_app_number] => 15/201966 [patent_app_country] => US [patent_app_date] => 2016-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 10987 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201966 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/201966
Multi-functional portable power charger Jul 4, 2016 Issued
Array ( [id] => 14983079 [patent_doc_number] => 10445457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-15 [patent_title] => Methods, systems, and articles of manufacture for implementing a physical design of an electronic design with DFM and design specification awareness [patent_app_type] => utility [patent_app_number] => 15/199304 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199304
Methods, systems, and articles of manufacture for implementing a physical design of an electronic design with DFM and design specification awareness Jun 29, 2016 Issued
Array ( [id] => 12146870 [patent_doc_number] => 09881123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-30 [patent_title] => 'Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact' [patent_app_type] => utility [patent_app_number] => 15/198635 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 11632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198635 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/198635
Method and system for timing analysis with adaptive timing window optimization for determining signal integrity impact Jun 29, 2016 Issued
Array ( [id] => 14799041 [patent_doc_number] => 10402525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Methods, systems, and articles of manufacture for implementing an electronic design with transistor level satisfiability models [patent_app_type] => utility [patent_app_number] => 15/199854 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199854 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199854
Methods, systems, and articles of manufacture for implementing an electronic design with transistor level satisfiability models Jun 29, 2016 Issued
Array ( [id] => 13767885 [patent_doc_number] => 10176288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-08 [patent_title] => System and method for placing components in an electronic circuit design [patent_app_type] => utility [patent_app_number] => 15/198734 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/198734
System and method for placing components in an electronic circuit design Jun 29, 2016 Issued
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