Search

Taylor V Oh

Examiner (ID: 8206, Phone: (571)272-0689 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1622, 1711, 1625, 1621, 1623
Total Applications
2574
Issued Applications
1814
Pending Applications
225
Abandoned Applications
535

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18440249 [patent_doc_number] => 20230187544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => ASSEMBLING OF MOLECULES ON A 2D MATERIAL AND AN ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/105497 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105497 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105497
Assembling of molecules on a 2D material and an electronic device Feb 2, 2023 Issued
Array ( [id] => 19229717 [patent_doc_number] => 12009361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Protection devices with trigger devices and methods of formation thereof [patent_app_type] => utility [patent_app_number] => 18/100043 [patent_app_country] => US [patent_app_date] => 2023-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 54 [patent_no_of_words] => 11139 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100043 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100043
Protection devices with trigger devices and methods of formation thereof Jan 22, 2023 Issued
Array ( [id] => 18395536 [patent_doc_number] => 20230163757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => FINFET THYRISTORS WITH EMBEDDED TRANSISTOR CONTROL FOR PROTECTING HIGH-SPEED COMMUNICATION SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/157550 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18157550 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/157550
FINFET THYRISTORS WITH EMBEDDED TRANSISTOR CONTROL FOR PROTECTING HIGH-SPEED COMMUNICATION SYSTEMS Jan 19, 2023 Pending
Array ( [id] => 18969383 [patent_doc_number] => 11903195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Openings layout of three-dimensional memory device [patent_app_type] => utility [patent_app_number] => 18/156619 [patent_app_country] => US [patent_app_date] => 2023-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10429 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156619 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/156619
Openings layout of three-dimensional memory device Jan 18, 2023 Issued
Array ( [id] => 18296202 [patent_doc_number] => 20230105888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/063361 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063361 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063361
Method of manufacturing semiconductor device and semiconductor device Dec 7, 2022 Issued
Array ( [id] => 19061473 [patent_doc_number] => 11940702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Composite oxide semiconductor, semiconductor device using the composite oxide semiconductor, and display device including the semiconductor device [patent_app_type] => utility [patent_app_number] => 17/994481 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 81 [patent_no_of_words] => 33169 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994481
Composite oxide semiconductor, semiconductor device using the composite oxide semiconductor, and display device including the semiconductor device Nov 27, 2022 Issued
Array ( [id] => 18999261 [patent_doc_number] => 11916117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Semiconductor Schottky rectifier device [patent_app_type] => utility [patent_app_number] => 17/985046 [patent_app_country] => US [patent_app_date] => 2022-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 42 [patent_no_of_words] => 7116 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17985046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/985046
Semiconductor Schottky rectifier device Nov 9, 2022 Issued
Array ( [id] => 19370556 [patent_doc_number] => 12062650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Vacuum channel electronic element, optical transmission circuit, and laminated chip [patent_app_type] => utility [patent_app_number] => 18/051135 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 13860 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18051135 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/051135
Vacuum channel electronic element, optical transmission circuit, and laminated chip Oct 30, 2022 Issued
Array ( [id] => 18211743 [patent_doc_number] => 20230058006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SEMICONDUCTOR DEVICE WITH ASYMMETRIC GATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/976876 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976876 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/976876
Semiconductor device with asymmetric gate structure Oct 30, 2022 Issued
Array ( [id] => 18211091 [patent_doc_number] => 20230057354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME [patent_app_type] => utility [patent_app_number] => 18/045415 [patent_app_country] => US [patent_app_date] => 2022-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18045415 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/045415
Doped polar layers and semiconductor device incorporating same Oct 9, 2022 Issued
Array ( [id] => 19341491 [patent_doc_number] => 12051688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Manufacturing method and semiconductor device [patent_app_type] => utility [patent_app_number] => 18/261796 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 34 [patent_no_of_words] => 15576 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 523 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18261796 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/261796
Manufacturing method and semiconductor device Sep 26, 2022 Issued
Array ( [id] => 18546397 [patent_doc_number] => 11719745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Method of operating semiconductor device [patent_app_type] => utility [patent_app_number] => 17/899662 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 33 [patent_no_of_words] => 17815 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 530 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899662
Method of operating semiconductor device Aug 30, 2022 Issued
Array ( [id] => 18991243 [patent_doc_number] => 20240063212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => INTEGRATED CIRCUIT STRUCTURE WITH DIODE OVER LATERAL BIPOLAR TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/890725 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890725 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/890725
INTEGRATED CIRCUIT STRUCTURE WITH DIODE OVER LATERAL BIPOLAR TRANSISTOR Aug 17, 2022 Pending
Array ( [id] => 18061750 [patent_doc_number] => 20220392837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => THIN FILM BASED PASSIVE DEVICES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/888532 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6741 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17888532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/888532
Thin film based passive devices and methods of forming the same Aug 15, 2022 Issued
Array ( [id] => 18040406 [patent_doc_number] => 20220384623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/886612 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886612
Semiconductor device Aug 11, 2022 Issued
Array ( [id] => 18349640 [patent_doc_number] => 20230137751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => BIPOLAR JUNCTION TRANSISTORS WITH A BASE LAYER PARTICIPATING IN A DIODE [patent_app_type] => utility [patent_app_number] => 17/872047 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872047 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872047
BIPOLAR JUNCTION TRANSISTORS WITH A BASE LAYER PARTICIPATING IN A DIODE Jul 24, 2022 Pending
Array ( [id] => 18680179 [patent_doc_number] => 20230317837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => POWER SEMICONDUCTOR DEVICE WITH REDUCED LOSS AND MANUFACTURING METHOD THE SAME [patent_app_type] => utility [patent_app_number] => 17/872212 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872212 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872212
Power semiconductor device with reduced loss and manufacturing method the same Jul 24, 2022 Issued
Array ( [id] => 18999293 [patent_doc_number] => 11916149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Doped polar layers and semiconductor device incorporating same [patent_app_type] => utility [patent_app_number] => 17/814330 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 26369 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814330 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/814330
Doped polar layers and semiconductor device incorporating same Jul 21, 2022 Issued
Array ( [id] => 18782342 [patent_doc_number] => 11824109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance [patent_app_type] => utility [patent_app_number] => 17/868836 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868836 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868836
Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance Jul 19, 2022 Issued
Array ( [id] => 17986245 [patent_doc_number] => 20220352282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/868328 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868328 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868328
DISPLAY DEVICE Jul 18, 2022 Abandoned
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