Taylor V Oh
Examiner (ID: 8206, Phone: (571)272-0689 , Office: P/1625 )
Most Active Art Unit | 1625 |
Art Unit(s) | 1622, 1711, 1625, 1621, 1623 |
Total Applications | 2574 |
Issued Applications | 1814 |
Pending Applications | 225 |
Abandoned Applications | 535 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 9191621
[patent_doc_number] => 20130330936
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-12-12
[patent_title] => 'METHOD OF DEPOSITION OF Al2O3/SiO2 STACKS, FROM ALUMINIUM AND SILICON PRECURSORS'
[patent_app_type] => utility
[patent_app_number] => 13/984045
[patent_app_country] => US
[patent_app_date] => 2011-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5686
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13984045
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/984045 | METHOD OF DEPOSITION OF Al2O3/SiO2 STACKS, FROM ALUMINIUM AND SILICON PRECURSORS | Dec 14, 2011 | Abandoned |
Array
(
[id] => 8049433
[patent_doc_number] => 20120074455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-29
[patent_title] => 'LED PACKAGE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 13/300630
[patent_app_country] => US
[patent_app_date] => 2011-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1705
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0074/20120074455.pdf
[firstpage_image] =>[orig_patent_app_number] => 13300630
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/300630 | LED PACKAGE STRUCTURE | Nov 19, 2011 | Abandoned |
Array
(
[id] => 8826024
[patent_doc_number] => 20130127069
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-23
[patent_title] => 'MATRICES FOR RAPID ALIGNMENT OF GRAPHITIC STRUCTURES FOR STACKED CHIP COOLING APPLICATIONS'
[patent_app_type] => utility
[patent_app_number] => 13/298438
[patent_app_country] => US
[patent_app_date] => 2011-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9486
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13298438
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/298438 | MATRICES FOR RAPID ALIGNMENT OF GRAPHITIC STRUCTURES FOR STACKED CHIP COOLING APPLICATIONS | Nov 16, 2011 | Abandoned |
Array
(
[id] => 8499588
[patent_doc_number] => 20120298996
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-29
[patent_title] => 'Thin Film Transistor and Method for Manufacturing the Same'
[patent_app_type] => utility
[patent_app_number] => 13/291150
[patent_app_country] => US
[patent_app_date] => 2011-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2264
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13291150
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/291150 | Thin Film Transistor and Method for Manufacturing the Same | Nov 7, 2011 | Abandoned |
Array
(
[id] => 10845036
[patent_doc_number] => 08872216
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Organic light emitting device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/283090
[patent_app_country] => US
[patent_app_date] => 2011-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3859
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283090
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/283090 | Organic light emitting device and method for manufacturing the same | Oct 26, 2011 | Issued |
Array
(
[id] => 8566611
[patent_doc_number] => 20120329182
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-27
[patent_title] => 'SEMICONDUCTOR DEVICE MOUNTING METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/512955
[patent_app_country] => US
[patent_app_date] => 2011-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7111
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13512955
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/512955 | SEMICONDUCTOR DEVICE MOUNTING METHOD | Oct 25, 2011 | Abandoned |
Array
(
[id] => 8217276
[patent_doc_number] => 20120132968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-31
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/279060
[patent_app_country] => US
[patent_app_date] => 2011-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2866
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13279060
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/279060 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Oct 20, 2011 | Abandoned |
Array
(
[id] => 8274840
[patent_doc_number] => 20120168706
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-05
[patent_title] => 'RESISTANCE RANDOM ACCESS MEMORY'
[patent_app_type] => utility
[patent_app_number] => 13/276590
[patent_app_country] => US
[patent_app_date] => 2011-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5201
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13276590
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/276590 | RESISTANCE RANDOM ACCESS MEMORY | Oct 18, 2011 | Abandoned |
Array
(
[id] => 8753588
[patent_doc_number] => 20130087892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-11
[patent_title] => 'Electrical Connection for Chip Scale Packaging'
[patent_app_type] => utility
[patent_app_number] => 13/269310
[patent_app_country] => US
[patent_app_date] => 2011-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5080
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13269310
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/269310 | Electrical connection for chip scale packaging | Oct 6, 2011 | Issued |
Array
(
[id] => 8753552
[patent_doc_number] => 20130087856
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-11
[patent_title] => 'Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate'
[patent_app_type] => utility
[patent_app_number] => 13/253430
[patent_app_country] => US
[patent_app_date] => 2011-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4630
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13253430
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/253430 | Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate | Oct 4, 2011 | Abandoned |
Array
(
[id] => 8753621
[patent_doc_number] => 20130087925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-11
[patent_title] => 'Packaging Structures of Integrated Circuits'
[patent_app_type] => utility
[patent_app_number] => 13/253799
[patent_app_country] => US
[patent_app_date] => 2011-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2814
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13253799
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/253799 | Packaging Structures of Integrated Circuits | Oct 4, 2011 | Abandoned |
Array
(
[id] => 9778456
[patent_doc_number] => 08853663
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-07
[patent_title] => 'Nonvolatile memory device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 13/252690
[patent_app_country] => US
[patent_app_date] => 2011-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 11584
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13252690
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/252690 | Nonvolatile memory device and manufacturing method thereof | Oct 3, 2011 | Issued |
Array
(
[id] => 8612353
[patent_doc_number] => 20130017665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-17
[patent_title] => 'METHODS OF FORMING ISOLATION STRUCTURE AND SEMICONDUCTOR STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 13/380807
[patent_app_country] => US
[patent_app_date] => 2011-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3400
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13380807
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/380807 | METHODS OF FORMING ISOLATION STRUCTURE AND SEMICONDUCTOR STRUCTURE | Aug 4, 2011 | Abandoned |
Array
(
[id] => 8582844
[patent_doc_number] => 20130001665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-03
[patent_title] => 'MOSFET AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/379433
[patent_app_country] => US
[patent_app_date] => 2011-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4729
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13379433
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/379433 | MOSFET and method for manufacturing the same | Aug 1, 2011 | Issued |
Array
(
[id] => 11807141
[patent_doc_number] => 09548224
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-17
[patent_title] => 'Method and apparatus to control surface texture modification of silicon wafers for photovoltaic cell devices'
[patent_app_type] => utility
[patent_app_number] => 13/696730
[patent_app_country] => US
[patent_app_date] => 2011-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4826
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13696730
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/696730 | Method and apparatus to control surface texture modification of silicon wafers for photovoltaic cell devices | May 10, 2011 | Issued |
Array
(
[id] => 8829379
[patent_doc_number] => 20130130424
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-23
[patent_title] => 'PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER'
[patent_app_type] => utility
[patent_app_number] => 13/695980
[patent_app_country] => US
[patent_app_date] => 2011-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 1260
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13695980
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/695980 | PROCESS FOR MINIMIZING CHIPPING WHEN SEPARATING MEMS DIES ON A WAFER | May 2, 2011 | Abandoned |
Array
(
[id] => 7564752
[patent_doc_number] => 20110284815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-11-24
[patent_title] => 'PHASE-CHANGE MEMORY DEVICES HAVING STRESS RELIEF BUFFERS'
[patent_app_type] => utility
[patent_app_number] => 13/070648
[patent_app_country] => US
[patent_app_date] => 2011-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8188
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0284/20110284815.pdf
[firstpage_image] =>[orig_patent_app_number] => 13070648
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/070648 | PHASE-CHANGE MEMORY DEVICES HAVING STRESS RELIEF BUFFERS | Mar 23, 2011 | Abandoned |
Array
(
[id] => 8767566
[patent_doc_number] => 20130095603
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-18
[patent_title] => 'METHOD FOR THE TREATMENT OF A METAL CONTACT FORMED ON A SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/634498
[patent_app_country] => US
[patent_app_date] => 2011-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4096
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13634498
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/634498 | METHOD FOR THE TREATMENT OF A METAL CONTACT FORMED ON A SUBSTRATE | Mar 10, 2011 | Abandoned |
Array
(
[id] => 8656978
[patent_doc_number] => 20130037807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-14
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/583311
[patent_app_country] => US
[patent_app_date] => 2011-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8404
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13583311
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/583311 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Mar 9, 2011 | Abandoned |
Array
(
[id] => 8379790
[patent_doc_number] => 20120223416
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-09-06
[patent_title] => 'THIN-FILM SEMICONDUCTOR COMPONENT WITH PROTECTION DIODE STRUCTURE AND METHOD FOR PRODUCING A THIN-FILM SEMICONDUCTOR COMPONENT'
[patent_app_type] => utility
[patent_app_number] => 13/497979
[patent_app_country] => US
[patent_app_date] => 2010-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5758
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13497979
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/497979 | THIN-FILM SEMICONDUCTOR COMPONENT WITH PROTECTION DIODE STRUCTURE AND METHOD FOR PRODUCING A THIN-FILM SEMICONDUCTOR COMPONENT | Nov 10, 2010 | Abandoned |