Search

Taylor V Oh

Examiner (ID: 8206, Phone: (571)272-0689 , Office: P/1625 )

Most Active Art Unit
1625
Art Unit(s)
1622, 1711, 1625, 1621, 1623
Total Applications
2574
Issued Applications
1814
Pending Applications
225
Abandoned Applications
535

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17676788 [patent_doc_number] => 20220189955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => SEMICONDUCTOR DEVICE WITH CONTROLLABLE CHANNEL LENGTH AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/689364 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/689364
Semiconductor device with controllable channel length and manufacturing method thereof Mar 7, 2022 Issued
Array ( [id] => 18222162 [patent_doc_number] => 20230061156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => FIN-BASED LATERAL BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/687741 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17687741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/687741
Fin-based lateral bipolar junction transistor with reduced base resistance and method Mar 6, 2022 Issued
Array ( [id] => 19079553 [patent_doc_number] => 11948933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Semiconductor devices and methods of manufacturing semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/650451 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650451
Semiconductor devices and methods of manufacturing semiconductor devices Feb 8, 2022 Issued
Array ( [id] => 18296831 [patent_doc_number] => 20230106517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => SRAM CELL STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/588509 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588509
SRAM CELL STRUCTURE Jan 30, 2022 Pending
Array ( [id] => 18735799 [patent_doc_number] => 11804541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Bipolar transistor structure with emitter/collector contact to doped semiconductor well and related methods [patent_app_type] => utility [patent_app_number] => 17/578011 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578011 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578011
Bipolar transistor structure with emitter/collector contact to doped semiconductor well and related methods Jan 17, 2022 Issued
Array ( [id] => 17738168 [patent_doc_number] => 20220223630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => SEMICONDUCTOR DEVICE WITH MULTIPLE ZERO DIFFERENTIAL TRANSCONDUCTANCE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/575732 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575732
SEMICONDUCTOR DEVICE WITH MULTIPLE ZERO DIFFERENTIAL TRANSCONDUCTANCE AND METHOD OF MANUFACTURING SAME Jan 13, 2022 Pending
Array ( [id] => 19261077 [patent_doc_number] => 12021144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Method of manufacturing a semiconductor device and a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/572366 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 10597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572366 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572366
Method of manufacturing a semiconductor device and a semiconductor device Jan 9, 2022 Issued
Array ( [id] => 17566923 [patent_doc_number] => 20220131072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => MEMORY DEVICE WITH COMPOSITE SPACER [patent_app_type] => utility [patent_app_number] => 17/572599 [patent_app_country] => US [patent_app_date] => 2022-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572599 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572599
Memory device with composite spacer Jan 9, 2022 Issued
Array ( [id] => 17765114 [patent_doc_number] => 20220238727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => ZENER DIODE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/571401 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571401
ZENER DIODE AND MANUFACTURING METHOD THEREOF Jan 6, 2022 Abandoned
Array ( [id] => 18625758 [patent_doc_number] => 11758825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Method of manufacturing magnetoresistive random access memory device [patent_app_type] => utility [patent_app_number] => 17/567211 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5247 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567211
Method of manufacturing magnetoresistive random access memory device Jan 2, 2022 Issued
Array ( [id] => 17551768 [patent_doc_number] => 20220123110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => VERTICAL TUNNEL FIELD-EFFECT TRANSISTOR WITH U-SHAPED GATE AND BAND ALIGNER [patent_app_type] => utility [patent_app_number] => 17/565254 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565254 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565254
VERTICAL TUNNEL FIELD-EFFECT TRANSISTOR WITH U-SHAPED GATE AND BAND ALIGNER Dec 28, 2021 Pending
Array ( [id] => 17551800 [patent_doc_number] => 20220123142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR DEVICE WITH LATERAL TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/563141 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563141
Semiconductor device with lateral transistor Dec 27, 2021 Issued
Array ( [id] => 18040378 [patent_doc_number] => 20220384595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION MASK LAYOUT [patent_app_type] => utility [patent_app_number] => 17/560465 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560465 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560465
SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION MASK LAYOUT Dec 22, 2021 Pending
Array ( [id] => 18456505 [patent_doc_number] => 20230197787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => BIPOLAR TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/559085 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559085
Bipolar transistors Dec 21, 2021 Issued
Array ( [id] => 18223019 [patent_doc_number] => 20230062013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => BIPOLAR TRANSISTOR STRUCTURE ON SEMICONDUCTOR FIN AND METHODS TO FORM SAME [patent_app_type] => utility [patent_app_number] => 17/644939 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644939 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644939
Bipolar transistor structure on semiconductor fin and methods to form same Dec 16, 2021 Issued
Array ( [id] => 19245764 [patent_doc_number] => 12016229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Electroluminescent display-panel manufacturing method [patent_app_type] => utility [patent_app_number] => 17/546010 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 27865 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546010 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546010
Electroluminescent display-panel manufacturing method Dec 7, 2021 Issued
Array ( [id] => 17486248 [patent_doc_number] => 20220093752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => LATERALLY-DIFFUSED METAL-OXIDE SEMICONDUCTOR TRANSISTOR AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 17/457801 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457801
Laterally-diffused metal-oxide semiconductor transistor and method therefor Dec 5, 2021 Issued
Array ( [id] => 17752921 [patent_doc_number] => 20220231126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => ELECTROSTATIC DISCHARGE PROTECTION DEVICE [patent_app_type] => utility [patent_app_number] => 17/542728 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542728
Electrostatic discharge protection device Dec 5, 2021 Issued
Array ( [id] => 18222723 [patent_doc_number] => 20230061717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => LATERAL BIPOLAR TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/533805 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17533805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/533805
Lateral bipolar transistor Nov 22, 2021 Issued
Array ( [id] => 19079623 [patent_doc_number] => 11949004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Lateral bipolar transistors with gate structure aligned to extrinsic base [patent_app_type] => utility [patent_app_number] => 17/533882 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3483 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17533882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/533882
Lateral bipolar transistors with gate structure aligned to extrinsic base Nov 22, 2021 Issued
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