Search

Tejis A. Daya

Examiner (ID: 4856, Phone: (571)270-7817 , Office: P/2472 )

Most Active Art Unit
2472
Art Unit(s)
2472
Total Applications
730
Issued Applications
591
Pending Applications
66
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 904913 [patent_doc_number] => 07340592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Executing a translated block of instructions and branching to correction code when expected top of stack does not match actual top of stack to adjust stack at execution time to continue executing without restarting translating' [patent_app_type] => utility [patent_app_number] => 09/676175 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2389 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340592.pdf [firstpage_image] =>[orig_patent_app_number] => 09676175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676175
Executing a translated block of instructions and branching to correction code when expected top of stack does not match actual top of stack to adjust stack at execution time to continue executing without restarting translating Sep 28, 2000 Issued
Array ( [id] => 937571 [patent_doc_number] => 06976151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Decoding an instruction portion and forwarding part of the portion to a first destination, re-encoding a different part of the portion and forwarding to a second destination' [patent_app_type] => utility [patent_app_number] => 09/675816 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2537 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976151.pdf [firstpage_image] =>[orig_patent_app_number] => 09675816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675816
Decoding an instruction portion and forwarding part of the portion to a first destination, re-encoding a different part of the portion and forwarding to a second destination Sep 27, 2000 Issued
Array ( [id] => 7615391 [patent_doc_number] => 06948056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages' [patent_app_type] => utility [patent_app_number] => 09/675066 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2456 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/948/06948056.pdf [firstpage_image] =>[orig_patent_app_number] => 09675066 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675066
Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages Sep 27, 2000 Issued
Array ( [id] => 832532 [patent_doc_number] => 07401204 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-15 [patent_title] => 'Parallel Processor efficiently executing variable instruction word' [patent_app_type] => utility [patent_app_number] => 09/654527 [patent_app_country] => US [patent_app_date] => 2000-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 15053 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/401/07401204.pdf [firstpage_image] =>[orig_patent_app_number] => 09654527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/654527
Parallel Processor efficiently executing variable instruction word Aug 31, 2000 Issued
Array ( [id] => 809985 [patent_doc_number] => 07421572 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-09-02 [patent_title] => 'Branch instruction for processor with branching dependent on a specified bit in a register' [patent_app_type] => utility [patent_app_number] => 10/069195 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4749 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421572.pdf [firstpage_image] =>[orig_patent_app_number] => 10069195 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/069195
Branch instruction for processor with branching dependent on a specified bit in a register Aug 30, 2000 Issued
Array ( [id] => 559536 [patent_doc_number] => 07178013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-13 [patent_title] => 'Repeat function for processing of repetitive instruction streams' [patent_app_type] => utility [patent_app_number] => 09/607815 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3777 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/178/07178013.pdf [firstpage_image] =>[orig_patent_app_number] => 09607815 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607815
Repeat function for processing of repetitive instruction streams Jun 29, 2000 Issued
Array ( [id] => 912233 [patent_doc_number] => 07334115 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-19 [patent_title] => 'Detection, recovery and prevention of bogus branches' [patent_app_type] => utility [patent_app_number] => 09/608512 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3460 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/334/07334115.pdf [firstpage_image] =>[orig_patent_app_number] => 09608512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608512
Detection, recovery and prevention of bogus branches Jun 29, 2000 Issued
09/606652 Method and apparatus for providing real-time operation in a personal computer system Jun 27, 2000 Abandoned
Array ( [id] => 852099 [patent_doc_number] => 07383424 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-03 [patent_title] => 'Computer architecture containing processor and decoupled coprocessor' [patent_app_type] => utility [patent_app_number] => 09/762981 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 13103 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/383/07383424.pdf [firstpage_image] =>[orig_patent_app_number] => 09762981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/762981
Computer architecture containing processor and decoupled coprocessor Jun 14, 2000 Issued
Array ( [id] => 761886 [patent_doc_number] => 07020766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-28 [patent_title] => 'Processing essential and non-essential code separately' [patent_app_type] => utility [patent_app_number] => 09/580755 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7552 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020766.pdf [firstpage_image] =>[orig_patent_app_number] => 09580755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/580755
Processing essential and non-essential code separately May 29, 2000 Issued
Array ( [id] => 659382 [patent_doc_number] => 07111155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'Digital signal processor computation core with input operand selection from operand bus for dual operations' [patent_app_type] => utility [patent_app_number] => 09/570108 [patent_app_country] => US [patent_app_date] => 2000-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 9645 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111155.pdf [firstpage_image] =>[orig_patent_app_number] => 09570108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/570108
Digital signal processor computation core with input operand selection from operand bus for dual operations May 11, 2000 Issued
Array ( [id] => 553821 [patent_doc_number] => 07174443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-06 [patent_title] => 'Run-time reconfiguration method for programmable units' [patent_app_type] => utility [patent_app_number] => 09/494567 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3238 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/174/07174443.pdf [firstpage_image] =>[orig_patent_app_number] => 09494567 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/494567
Run-time reconfiguration method for programmable units Jan 30, 2000 Issued
Array ( [id] => 7605697 [patent_doc_number] => 07100025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-29 [patent_title] => 'Apparatus and method for performing single-instruction multiple-data instructions' [patent_app_type] => utility [patent_app_number] => 09/491810 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3351 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/100/07100025.pdf [firstpage_image] =>[orig_patent_app_number] => 09491810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/491810
Apparatus and method for performing single-instruction multiple-data instructions Jan 27, 2000 Issued
Array ( [id] => 1214435 [patent_doc_number] => 06715060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data' [patent_app_type] => B1 [patent_app_number] => 09/493986 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7228 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715060.pdf [firstpage_image] =>[orig_patent_app_number] => 09493986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/493986
Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data Jan 27, 2000 Issued
Array ( [id] => 684742 [patent_doc_number] => 07085914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-01 [patent_title] => 'Methods for renaming stack references to processor registers' [patent_app_type] => utility [patent_app_number] => 09/492544 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7166 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085914.pdf [firstpage_image] =>[orig_patent_app_number] => 09492544 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492544
Methods for renaming stack references to processor registers Jan 26, 2000 Issued
Array ( [id] => 1314594 [patent_doc_number] => 06622238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'System and method for providing predicate data' [patent_app_type] => B1 [patent_app_number] => 09/490395 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8074 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622238.pdf [firstpage_image] =>[orig_patent_app_number] => 09490395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/490395
System and method for providing predicate data Jan 23, 2000 Issued
Array ( [id] => 1214451 [patent_doc_number] => 06715064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method and apparatus for performing sequential executions of elements in cooperation with a transform' [patent_app_type] => B1 [patent_app_number] => 09/489072 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4592 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715064.pdf [firstpage_image] =>[orig_patent_app_number] => 09489072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/489072
Method and apparatus for performing sequential executions of elements in cooperation with a transform Jan 20, 2000 Issued
Array ( [id] => 1166242 [patent_doc_number] => 06772322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-03 [patent_title] => 'Method and apparatus to monitor the performance of a processor' [patent_app_type] => B1 [patent_app_number] => 09/489141 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4111 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/772/06772322.pdf [firstpage_image] =>[orig_patent_app_number] => 09489141 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/489141
Method and apparatus to monitor the performance of a processor Jan 20, 2000 Issued
Array ( [id] => 1339447 [patent_doc_number] => 06601162 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Processor which executes pipeline processing having a plurality of stages and which has an operand bypass predicting function' [patent_app_type] => B1 [patent_app_number] => 09/487763 [patent_app_country] => US [patent_app_date] => 2000-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9533 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601162.pdf [firstpage_image] =>[orig_patent_app_number] => 09487763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/487763
Processor which executes pipeline processing having a plurality of stages and which has an operand bypass predicting function Jan 18, 2000 Issued
Array ( [id] => 943568 [patent_doc_number] => 06970996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-29 [patent_title] => 'Operand queue for use in a floating point unit to reduce read-after-write latency and method of operation' [patent_app_type] => utility [patent_app_number] => 09/477093 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4825 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/970/06970996.pdf [firstpage_image] =>[orig_patent_app_number] => 09477093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477093
Operand queue for use in a floating point unit to reduce read-after-write latency and method of operation Jan 3, 2000 Issued
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