Search

Tejis A. Daya

Examiner (ID: 4856, Phone: (571)270-7817 , Office: P/2472 )

Most Active Art Unit
2472
Art Unit(s)
2472
Total Applications
730
Issued Applications
591
Pending Applications
66
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 524721 [patent_doc_number] => 07197627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-27 [patent_title] => 'Multiple processor arrangement for conserving power' [patent_app_type] => utility [patent_app_number] => 09/830719 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2155 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197627.pdf [firstpage_image] =>[orig_patent_app_number] => 09830719 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/830719
Multiple processor arrangement for conserving power Oct 24, 1999 Issued
Array ( [id] => 1337241 [patent_doc_number] => 06604188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Pipeline replay support for multi-cycle operations wherein all VLIW instructions are flushed upon detection of a multi-cycle atom operation in a VLIW instruction' [patent_app_type] => B1 [patent_app_number] => 09/421972 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8148 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604188.pdf [firstpage_image] =>[orig_patent_app_number] => 09421972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421972
Pipeline replay support for multi-cycle operations wherein all VLIW instructions are flushed upon detection of a multi-cycle atom operation in a VLIW instruction Oct 19, 1999 Issued
Array ( [id] => 6698171 [patent_doc_number] => 20030110365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'CENTRAL PROCESSING UNIT AND SYSTEM HAVING A PREFETCH QUEUE AND A COMMAND CACHE TO PERFORM AN EFFICIENT INFORMATION READING OPERATION' [patent_app_type] => new [patent_app_number] => 09/421008 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5293 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110365.pdf [firstpage_image] =>[orig_patent_app_number] => 09421008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421008
Central processing unit and system having a prefetch queue and a command cache to perform an efficient information reading operation Oct 19, 1999 Issued
Array ( [id] => 1186685 [patent_doc_number] => 06738892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Use of enable bits to control execution of selected instructions' [patent_app_type] => B1 [patent_app_number] => 09/421615 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 9378 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/738/06738892.pdf [firstpage_image] =>[orig_patent_app_number] => 09421615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421615
Use of enable bits to control execution of selected instructions Oct 19, 1999 Issued
Array ( [id] => 1229222 [patent_doc_number] => 06701426 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Switching between a plurality of branch prediction processes based on which instruction set is operational wherein branch history data structures are the same for the plurality of instruction sets' [patent_app_type] => B1 [patent_app_number] => 09/425037 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2960 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701426.pdf [firstpage_image] =>[orig_patent_app_number] => 09425037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/425037
Switching between a plurality of branch prediction processes based on which instruction set is operational wherein branch history data structures are the same for the plurality of instruction sets Oct 18, 1999 Issued
Array ( [id] => 1218226 [patent_doc_number] => 06711670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'System and method for detecting data hazards within an instruction group of a compiled computer program' [patent_app_type] => B1 [patent_app_number] => 09/417582 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8829 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711670.pdf [firstpage_image] =>[orig_patent_app_number] => 09417582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417582
System and method for detecting data hazards within an instruction group of a compiled computer program Oct 13, 1999 Issued
Array ( [id] => 7611332 [patent_doc_number] => 06904510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-07 [patent_title] => 'Data processor having a respective multiplexer for each particular field' [patent_app_type] => utility [patent_app_number] => 09/414458 [patent_app_country] => US [patent_app_date] => 1999-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5035 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904510.pdf [firstpage_image] =>[orig_patent_app_number] => 09414458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414458
Data processor having a respective multiplexer for each particular field Oct 6, 1999 Issued
Array ( [id] => 1348135 [patent_doc_number] => 06598151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Stack Pointer Management' [patent_app_type] => B1 [patent_app_number] => 09/411416 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 9085 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598151.pdf [firstpage_image] =>[orig_patent_app_number] => 09411416 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411416
Stack Pointer Management Sep 30, 1999 Issued
Array ( [id] => 6814993 [patent_doc_number] => 20030074543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'A PROCESSOR WITH APPARATUS FOR VERIFYING INSTRUCTION PARALLELISM' [patent_app_type] => new [patent_app_number] => 09/410731 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12637 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074543.pdf [firstpage_image] =>[orig_patent_app_number] => 09410731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410731
Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution Sep 30, 1999 Issued
Array ( [id] => 1112188 [patent_doc_number] => 06810475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Processor with pipeline conflict resolution using distributed arbitration and shadow registers' [patent_app_type] => B1 [patent_app_number] => 09/411434 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 12995 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810475.pdf [firstpage_image] =>[orig_patent_app_number] => 09411434 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411434
Processor with pipeline conflict resolution using distributed arbitration and shadow registers Sep 30, 1999 Issued
09/411340 SYSTEM AND METHOD FOR PERFORMING EXCEPTION HANDLING FOR BRANCH ADDRESS CALCULATIONS Sep 30, 1999 Abandoned
Array ( [id] => 1421408 [patent_doc_number] => 06542988 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Sending both a load instruction and retrieved data from a load buffer to an annex prior to forwarding the load data to register file' [patent_app_type] => B1 [patent_app_number] => 09/410842 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6014 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542988.pdf [firstpage_image] =>[orig_patent_app_number] => 09410842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410842
Sending both a load instruction and retrieved data from a load buffer to an annex prior to forwarding the load data to register file Sep 30, 1999 Issued
09/411824 FACILITATING PRECISE TRAP HANDLINg FOR SPECULATIVE AND OUT-OF-ORDER LOAD INSTRUCTIONS IN ACCORDANCE WITH AGE OF THE LOAD INSTRUCTIONS Sep 30, 1999 Abandoned
Array ( [id] => 1573799 [patent_doc_number] => 06499098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Processor with instruction qualifiers to control MMU operation' [patent_app_type] => B1 [patent_app_number] => 09/411408 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 11746 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499098.pdf [firstpage_image] =>[orig_patent_app_number] => 09411408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411408
Processor with instruction qualifiers to control MMU operation Sep 30, 1999 Issued
Array ( [id] => 940469 [patent_doc_number] => 06973559 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Scalable hypercube multiprocessor network for massive parallel processing' [patent_app_type] => utility [patent_app_number] => 09/408972 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/973/06973559.pdf [firstpage_image] =>[orig_patent_app_number] => 09408972 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408972
Scalable hypercube multiprocessor network for massive parallel processing Sep 28, 1999 Issued
Array ( [id] => 472872 [patent_doc_number] => 07234042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-19 [patent_title] => 'Identification bit at a predetermined instruction location that indicates whether the instruction is one or two independent operations and indicates the nature the operations executing in two processing channels' [patent_app_type] => utility [patent_app_number] => 09/395294 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3497 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/234/07234042.pdf [firstpage_image] =>[orig_patent_app_number] => 09395294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395294
Identification bit at a predetermined instruction location that indicates whether the instruction is one or two independent operations and indicates the nature the operations executing in two processing channels Sep 12, 1999 Issued
Array ( [id] => 536390 [patent_doc_number] => 07191317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-13 [patent_title] => 'System and method for selectively controlling operations in lanes' [patent_app_type] => utility [patent_app_number] => 09/395297 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4500 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191317.pdf [firstpage_image] =>[orig_patent_app_number] => 09395297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395297
System and method for selectively controlling operations in lanes Sep 12, 1999 Issued
Array ( [id] => 1431925 [patent_doc_number] => 06516409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Processor provided with a data value prediction circuit and a branch prediction circuit' [patent_app_type] => B1 [patent_app_number] => 09/385449 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4707 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516409.pdf [firstpage_image] =>[orig_patent_app_number] => 09385449 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385449
Processor provided with a data value prediction circuit and a branch prediction circuit Aug 29, 1999 Issued
Array ( [id] => 6717411 [patent_doc_number] => 20030028759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'EXCEPTION HANDLING FOR SIMD FLOATING POINT-INSTRUCTIONS' [patent_app_type] => new [patent_app_number] => 09/374052 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028759.pdf [firstpage_image] =>[orig_patent_app_number] => 09374052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/374052
Exception handling for SIMD floating point-instructions using a floating point status register to report exceptions Aug 12, 1999 Issued
Array ( [id] => 7633064 [patent_doc_number] => 06658556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction' [patent_app_type] => B1 [patent_app_number] => 09/364288 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4049 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658556.pdf [firstpage_image] =>[orig_patent_app_number] => 09364288 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364288
Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction Jul 29, 1999 Issued
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