Search

Tejis A. Daya

Examiner (ID: 4856, Phone: (571)270-7817 , Office: P/2472 )

Most Active Art Unit
2472
Art Unit(s)
2472
Total Applications
730
Issued Applications
591
Pending Applications
66
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 503869 [patent_doc_number] => 07213132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'System and method for providing predicate data to multiple pipeline stages' [patent_app_type] => utility [patent_app_number] => 10/648960 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8112 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/213/07213132.pdf [firstpage_image] =>[orig_patent_app_number] => 10648960 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/648960
System and method for providing predicate data to multiple pipeline stages Aug 26, 2003 Issued
Array ( [id] => 809951 [patent_doc_number] => 07421555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'System, device, and method for managing file security attributes in a computer file storage system' [patent_app_type] => utility [patent_app_number] => 10/646365 [patent_app_country] => US [patent_app_date] => 2003-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7376 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421555.pdf [firstpage_image] =>[orig_patent_app_number] => 10646365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/646365
System, device, and method for managing file security attributes in a computer file storage system Aug 21, 2003 Issued
Array ( [id] => 806145 [patent_doc_number] => 07424600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-09 [patent_title] => 'Information processing apparatus, information processing method, and program conversion apparatus, in which stack memory is used with improved efficiency' [patent_app_type] => utility [patent_app_number] => 10/624901 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11925 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/424/07424600.pdf [firstpage_image] =>[orig_patent_app_number] => 10624901 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/624901
Information processing apparatus, information processing method, and program conversion apparatus, in which stack memory is used with improved efficiency Jul 22, 2003 Issued
Array ( [id] => 7243899 [patent_doc_number] => 20050080784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Data processing system' [patent_app_type] => utility [patent_app_number] => 10/611937 [patent_app_country] => US [patent_app_date] => 2003-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 27615 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20050080784.pdf [firstpage_image] =>[orig_patent_app_number] => 10611937 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/611937
Data processing system Jul 2, 2003 Abandoned
Array ( [id] => 7449175 [patent_doc_number] => 20040268095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Efficient implementation of null reference check' [patent_app_type] => new [patent_app_number] => 10/611283 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4440 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20040268095.pdf [firstpage_image] =>[orig_patent_app_number] => 10611283 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/611283
Efficient implementation of null reference check Jun 29, 2003 Abandoned
Array ( [id] => 900140 [patent_doc_number] => 07343479 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Method and apparatus for implementing two architectures in a chip' [patent_app_type] => utility [patent_app_number] => 10/602916 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2307 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/343/07343479.pdf [firstpage_image] =>[orig_patent_app_number] => 10602916 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602916
Method and apparatus for implementing two architectures in a chip Jun 24, 2003 Issued
Array ( [id] => 7393900 [patent_doc_number] => 20040030859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Processing system with interspersed processors and communication elements' [patent_app_type] => new [patent_app_number] => 10/602292 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 21188 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20040030859.pdf [firstpage_image] =>[orig_patent_app_number] => 10602292 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602292
Processing system with interspersed stall propagating processors and communication elements Jun 23, 2003 Issued
Array ( [id] => 7404810 [patent_doc_number] => 20040039897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Data processing device and electronic equipment' [patent_app_type] => new [patent_app_number] => 10/601136 [patent_app_country] => US [patent_app_date] => 2003-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9407 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20040039897.pdf [firstpage_image] =>[orig_patent_app_number] => 10601136 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/601136
Shift prefix instruction decoder for modifying register information necessary for decoding the target instruction Jun 19, 2003 Issued
Array ( [id] => 7472450 [patent_doc_number] => 20040199755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Apparatus and methods for exception handling for fused micro-operations by re-issue in the unfused format' [patent_app_type] => new [patent_app_number] => 10/407469 [patent_app_country] => US [patent_app_date] => 2003-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3523 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20040199755.pdf [firstpage_image] =>[orig_patent_app_number] => 10407469 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/407469
Apparatus and methods for exception handling for fused micro-operations by re-issue in the unfused format Apr 6, 2003 Abandoned
Array ( [id] => 6866399 [patent_doc_number] => 20030191925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Technique for reduced-tag dynamic scheduling' [patent_app_type] => new [patent_app_number] => 10/406475 [patent_app_country] => US [patent_app_date] => 2003-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3066 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20030191925.pdf [firstpage_image] =>[orig_patent_app_number] => 10406475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/406475
Technique for reduced-tag dynamic scheduling and reduced-tag prediction Apr 2, 2003 Issued
Array ( [id] => 7457177 [patent_doc_number] => 20040186984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Branch prediction in a data processing system' [patent_app_type] => new [patent_app_number] => 10/391186 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20040186984.pdf [firstpage_image] =>[orig_patent_app_number] => 10391186 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/391186
Branch prediction in a data processing system utilizing a cache of previous static predictions Mar 18, 2003 Issued
Array ( [id] => 7672128 [patent_doc_number] => 20040181651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Issue bandwidth in a multi-issue out-of-order processor' [patent_app_type] => new [patent_app_number] => 10/386349 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3161 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20040181651.pdf [firstpage_image] =>[orig_patent_app_number] => 10386349 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/386349
Issue bandwidth in a multi-issue out-of-order processor Mar 10, 2003 Abandoned
Array ( [id] => 7173461 [patent_doc_number] => 20040078413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Device for monitoring operation of processing circuit' [patent_app_type] => new [patent_app_number] => 10/348001 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3285 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078413.pdf [firstpage_image] =>[orig_patent_app_number] => 10348001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/348001
Device for monitoring operation of processing circuit Jan 21, 2003 Abandoned
Array ( [id] => 7309066 [patent_doc_number] => 20040117598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network' [patent_app_type] => new [patent_app_number] => 10/318513 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7160 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20040117598.pdf [firstpage_image] =>[orig_patent_app_number] => 10318513 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318513
Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network Dec 11, 2002 Issued
Array ( [id] => 890567 [patent_doc_number] => 07353371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Circuit to extract nonadjacent bits from data packets' [patent_app_type] => utility [patent_app_number] => 10/314194 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7018 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/353/07353371.pdf [firstpage_image] =>[orig_patent_app_number] => 10314194 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314194
Circuit to extract nonadjacent bits from data packets Dec 4, 2002 Issued
Array ( [id] => 7141050 [patent_doc_number] => 20050183091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Data processing system' [patent_app_type] => utility [patent_app_number] => 10/498293 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7630 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20050183091.pdf [firstpage_image] =>[orig_patent_app_number] => 10498293 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/498293
Data processing system Dec 4, 2002 Issued
Array ( [id] => 846206 [patent_doc_number] => 07389407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-17 [patent_title] => 'Central control system and method for using state information to model inflight pipelined instructions' [patent_app_type] => utility [patent_app_number] => 10/278559 [patent_app_country] => US [patent_app_date] => 2002-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 16557 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389407.pdf [firstpage_image] =>[orig_patent_app_number] => 10278559 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278559
Central control system and method for using state information to model inflight pipelined instructions Oct 22, 2002 Issued
Array ( [id] => 7393620 [patent_doc_number] => 20040030815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Data processing system and control method thereof' [patent_app_type] => new [patent_app_number] => 10/399360 [patent_app_country] => US [patent_app_date] => 2003-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14128 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20040030815.pdf [firstpage_image] =>[orig_patent_app_number] => 10399360 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/399360
Data processing system and control method utilizing a plurality of date transfer means Sep 5, 2002 Issued
Array ( [id] => 581919 [patent_doc_number] => 07159099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Streaming vector processor with reconfigurable interconnection switch' [patent_app_type] => utility [patent_app_number] => 10/184583 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3986 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/159/07159099.pdf [firstpage_image] =>[orig_patent_app_number] => 10184583 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184583
Streaming vector processor with reconfigurable interconnection switch Jun 27, 2002 Issued
Array ( [id] => 690830 [patent_doc_number] => 07080237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Register window flattening logic for dependency checking among instructions' [patent_app_type] => utility [patent_app_number] => 10/155391 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2644 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080237.pdf [firstpage_image] =>[orig_patent_app_number] => 10155391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155391
Register window flattening logic for dependency checking among instructions May 23, 2002 Issued
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