Search

Tejis A. Daya

Examiner (ID: 4856, Phone: (571)270-7817 , Office: P/2472 )

Most Active Art Unit
2472
Art Unit(s)
2472
Total Applications
730
Issued Applications
591
Pending Applications
66
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6822928 [patent_doc_number] => 20030221089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Microprocessor data manipulation matrix module' [patent_app_type] => new [patent_app_number] => 10/154774 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7849 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20030221089.pdf [firstpage_image] =>[orig_patent_app_number] => 10154774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154774
Microprocessor data manipulation matrix module May 22, 2002 Abandoned
Array ( [id] => 6771311 [patent_doc_number] => 20030217251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Prediction of load-store dependencies in a processing agent' [patent_app_type] => new [patent_app_number] => 10/146956 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4839 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20030217251.pdf [firstpage_image] =>[orig_patent_app_number] => 10146956 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146956
Prediction of load-store dependencies in a processing agent May 16, 2002 Issued
10/146651 Advanced configurable and extensible microprocessor architecture May 12, 2002 Abandoned
Array ( [id] => 685461 [patent_doc_number] => 07082520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Branch prediction utilizing both a branch target buffer and a multiple target table' [patent_app_type] => utility [patent_app_number] => 10/143621 [patent_app_country] => US [patent_app_date] => 2002-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3336 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/082/07082520.pdf [firstpage_image] =>[orig_patent_app_number] => 10143621 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/143621
Branch prediction utilizing both a branch target buffer and a multiple target table May 8, 2002 Issued
Array ( [id] => 6647698 [patent_doc_number] => 20030212878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Scaleable microprocessor architecture' [patent_app_type] => new [patent_app_number] => 10/139537 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20030212878.pdf [firstpage_image] =>[orig_patent_app_number] => 10139537 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/139537
Scaleable microprocessor architecture May 6, 2002 Abandoned
Array ( [id] => 6051460 [patent_doc_number] => 20020169942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'VLIW processor' [patent_app_type] => new [patent_app_number] => 10/137358 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6043 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20020169942.pdf [firstpage_image] =>[orig_patent_app_number] => 10137358 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/137358
VLIW processor May 2, 2002 Abandoned
Array ( [id] => 6665380 [patent_doc_number] => 20030204707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Real-time tracing microprocessor unit and operating method' [patent_app_type] => new [patent_app_number] => 10/063440 [patent_app_country] => US [patent_app_date] => 2002-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3069 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20030204707.pdf [firstpage_image] =>[orig_patent_app_number] => 10063440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/063440
Real-time tracing microprocessor unit and operating method Apr 23, 2002 Abandoned
Array ( [id] => 503883 [patent_doc_number] => 07213134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Using thread urgency in determining switch events in a temporal multithreaded processor unit' [patent_app_type] => utility [patent_app_number] => 10/092670 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2282 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/213/07213134.pdf [firstpage_image] =>[orig_patent_app_number] => 10092670 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092670
Using thread urgency in determining switch events in a temporal multithreaded processor unit Mar 5, 2002 Issued
Array ( [id] => 6836130 [patent_doc_number] => 20030163676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Daisy chain register read back' [patent_app_type] => new [patent_app_number] => 10/085642 [patent_app_country] => US [patent_app_date] => 2002-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6695 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163676.pdf [firstpage_image] =>[orig_patent_app_number] => 10085642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/085642
Reading a selected register in a series of computational units forming a processing pipeline upon expiration of a time delay Feb 27, 2002 Issued
Array ( [id] => 749438 [patent_doc_number] => 07032101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method and apparatus for prioritized instruction issue queue in a processor' [patent_app_type] => utility [patent_app_number] => 10/085606 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4639 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032101.pdf [firstpage_image] =>[orig_patent_app_number] => 10085606 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/085606
Method and apparatus for prioritized instruction issue queue in a processor Feb 25, 2002 Issued
10/069297 Microprocessor having an instruction format containing explicit timing information Feb 24, 2002 Abandoned
Array ( [id] => 1042168 [patent_doc_number] => 06870789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Modified retirement payload array' [patent_app_type] => utility [patent_app_number] => 10/071566 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6266 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870789.pdf [firstpage_image] =>[orig_patent_app_number] => 10071566 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/071566
Modified retirement payload array Feb 7, 2002 Issued
Array ( [id] => 6675864 [patent_doc_number] => 20030061467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Scoreboarding mechanism in a pipeline that includes replays and redirects' [patent_app_type] => new [patent_app_number] => 10/066941 [patent_app_country] => US [patent_app_date] => 2002-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 19274 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061467.pdf [firstpage_image] =>[orig_patent_app_number] => 10066941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/066941
Comparing operands of instructions against a replay scoreboard to detect an instruction replay and copying a replay scoreboard to an issue scoreboard Feb 3, 2002 Issued
Array ( [id] => 5926578 [patent_doc_number] => 20020116601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Method, a system and a computer program product for manipulating an instruction flow in a pipeline of a processor' [patent_app_type] => new [patent_app_number] => 10/066833 [patent_app_country] => US [patent_app_date] => 2002-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4431 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116601.pdf [firstpage_image] =>[orig_patent_app_number] => 10066833 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/066833
Method, a system and a computer program product for manipulating an instruction flow in a pipeline of a processor Feb 3, 2002 Abandoned
Array ( [id] => 6561328 [patent_doc_number] => 20020138711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Instruction path coprocessor synchronization' [patent_app_type] => new [patent_app_number] => 10/059443 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4312 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20020138711.pdf [firstpage_image] =>[orig_patent_app_number] => 10059443 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/059443
Instruction path coprocessor synchronization Jan 28, 2002 Abandoned
Array ( [id] => 6788979 [patent_doc_number] => 20030140218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'General purpose state machine' [patent_app_type] => new [patent_app_number] => 10/056326 [patent_app_country] => US [patent_app_date] => 2002-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4185 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20030140218.pdf [firstpage_image] =>[orig_patent_app_number] => 10056326 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/056326
General purpose state machine Jan 22, 2002 Abandoned
Array ( [id] => 6484919 [patent_doc_number] => 20020152368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Processor with value predictor' [patent_app_type] => new [patent_app_number] => 10/046982 [patent_app_country] => US [patent_app_date] => 2002-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5279 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20020152368.pdf [firstpage_image] =>[orig_patent_app_number] => 10046982 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/046982
Processor using a predicted result in executing a subsequent instruction regardless of whether a predicted value is true or false Jan 16, 2002 Issued
Array ( [id] => 7107137 [patent_doc_number] => 20050108438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Heterogeneous synergetic computing system' [patent_app_type] => utility [patent_app_number] => 10/498529 [patent_app_country] => US [patent_app_date] => 2001-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2683 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108438.pdf [firstpage_image] =>[orig_patent_app_number] => 10498529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/498529
Heterogeneous synergetic computing system Dec 12, 2001 Abandoned
Array ( [id] => 478335 [patent_doc_number] => 07231510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof' [patent_app_type] => utility [patent_app_number] => 10/007498 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5228 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231510.pdf [firstpage_image] =>[orig_patent_app_number] => 10007498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/007498
Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof Nov 12, 2001 Issued
Array ( [id] => 481332 [patent_doc_number] => 07228401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor' [patent_app_type] => utility [patent_app_number] => 10/054577 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6718 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/228/07228401.pdf [firstpage_image] =>[orig_patent_app_number] => 10054577 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/054577
Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor Nov 12, 2001 Issued
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