Search

Tejis A. Daya

Examiner (ID: 4856, Phone: (571)270-7817 , Office: P/2472 )

Most Active Art Unit
2472
Art Unit(s)
2472
Total Applications
730
Issued Applications
591
Pending Applications
66
Abandoned Applications
89

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6736981 [patent_doc_number] => 20030014616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Method and apparatus for pre-processing a data collection for use by a big-endian operating system' [patent_app_type] => new [patent_app_number] => 09/897348 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4230 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014616.pdf [firstpage_image] =>[orig_patent_app_number] => 09897348 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/897348
Method and apparatus for pre-processing a data collection for use by a big-endian operating system Jul 1, 2001 Abandoned
Array ( [id] => 649065 [patent_doc_number] => 07120783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'System and method for reading and writing a thread state in a multithreaded central processing unit' [patent_app_type] => utility [patent_app_number] => 09/888296 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 8105 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120783.pdf [firstpage_image] =>[orig_patent_app_number] => 09888296 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888296
System and method for reading and writing a thread state in a multithreaded central processing unit Jun 21, 2001 Issued
Array ( [id] => 596423 [patent_doc_number] => 07454600 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Method and apparatus for assigning thread priority in a processor or the like' [patent_app_type] => utility [patent_app_number] => 09/888273 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3463 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454600.pdf [firstpage_image] =>[orig_patent_app_number] => 09888273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888273
Method and apparatus for assigning thread priority in a processor or the like Jun 21, 2001 Issued
Array ( [id] => 731273 [patent_doc_number] => 07047396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-16 [patent_title] => 'Fixed length memory to memory arithmetic and architecture for a communications embedded processor system' [patent_app_type] => utility [patent_app_number] => 09/888295 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6294 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/047/07047396.pdf [firstpage_image] =>[orig_patent_app_number] => 09888295 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888295
Fixed length memory to memory arithmetic and architecture for a communications embedded processor system Jun 21, 2001 Issued
Array ( [id] => 6757492 [patent_doc_number] => 20030005269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Multi-precision barrel shifting' [patent_app_type] => new [patent_app_number] => 09/870458 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6585 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005269.pdf [firstpage_image] =>[orig_patent_app_number] => 09870458 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870458
Multi-precision barrel shifting May 31, 2001 Abandoned
Array ( [id] => 6819101 [patent_doc_number] => 20030070059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'System and method for performing efficient conditional vector operations for data parallel architectures' [patent_app_type] => new [patent_app_number] => 09/871301 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10115 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20030070059.pdf [firstpage_image] =>[orig_patent_app_number] => 09871301 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871301
System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values May 29, 2001 Issued
Array ( [id] => 562503 [patent_doc_number] => 07165169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Speculative branch target address cache with selective override by secondary predictor based on branch instruction type' [patent_app_type] => utility [patent_app_number] => 09/849799 [patent_app_country] => US [patent_app_date] => 2001-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 22654 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/165/07165169.pdf [firstpage_image] =>[orig_patent_app_number] => 09849799 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849799
Speculative branch target address cache with selective override by secondary predictor based on branch instruction type May 3, 2001 Issued
Array ( [id] => 633378 [patent_doc_number] => 07134005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte' [patent_app_type] => utility [patent_app_number] => 09/849658 [patent_app_country] => US [patent_app_date] => 2001-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 24009 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/134/07134005.pdf [firstpage_image] =>[orig_patent_app_number] => 09849658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849658
Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte May 3, 2001 Issued
Array ( [id] => 6161140 [patent_doc_number] => 20020147768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Data driven digital signal processor' [patent_app_type] => new [patent_app_number] => 09/826134 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2860 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20020147768.pdf [firstpage_image] =>[orig_patent_app_number] => 09826134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826134
Different register data indicators for each of a plurality of central processing units Apr 3, 2001 Issued
Array ( [id] => 6451481 [patent_doc_number] => 20020129229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Microinstruction sequencer stack' [patent_app_type] => new [patent_app_number] => 09/750093 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5754 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20020129229.pdf [firstpage_image] =>[orig_patent_app_number] => 09750093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750093
Microinstruction sequencer stack Dec 28, 2000 Abandoned
Array ( [id] => 6648703 [patent_doc_number] => 20020087838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Processor pipeline stall apparatus and method of operation' [patent_app_type] => new [patent_app_number] => 09/751331 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5785 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087838.pdf [firstpage_image] =>[orig_patent_app_number] => 09751331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751331
Processor pipeline cache miss apparatus and method for operation Dec 28, 2000 Issued
Array ( [id] => 799033 [patent_doc_number] => 07428627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Method and apparatus for predicting values in a processor having a plurality of prediction modes' [patent_app_type] => utility [patent_app_number] => 09/750150 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 6679 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/428/07428627.pdf [firstpage_image] =>[orig_patent_app_number] => 09750150 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750150
Method and apparatus for predicting values in a processor having a plurality of prediction modes Dec 28, 2000 Issued
Array ( [id] => 6648633 [patent_doc_number] => 20020087829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Re-targetable communication system' [patent_app_type] => new [patent_app_number] => 09/751432 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4318 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087829.pdf [firstpage_image] =>[orig_patent_app_number] => 09751432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751432
Re-targetable communication system Dec 28, 2000 Abandoned
Array ( [id] => 6648785 [patent_doc_number] => 20020087848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'System and method for executing conditional branch instructions in a data processor' [patent_app_type] => new [patent_app_number] => 09/751410 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7241 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087848.pdf [firstpage_image] =>[orig_patent_app_number] => 09751410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751410
Executing conditional branch instructions in a data processor having a clustered architecture Dec 28, 2000 Issued
Array ( [id] => 5861273 [patent_doc_number] => 20020124158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Virtual r0 register' [patent_app_type] => new [patent_app_number] => 09/752243 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1900 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124158.pdf [firstpage_image] =>[orig_patent_app_number] => 09752243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752243
Virtual r0 register Dec 27, 2000 Abandoned
Array ( [id] => 6741758 [patent_doc_number] => 20030159127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Method and apparatus for producing instruction words to trigger functional units in a processor' [patent_app_type] => new [patent_app_number] => 09/750733 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1054 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20030159127.pdf [firstpage_image] =>[orig_patent_app_number] => 09750733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750733
Method and apparatus for producing instruction words to trigger functional units in a processor Dec 26, 2000 Abandoned
Array ( [id] => 6876972 [patent_doc_number] => 20010007125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Computer system with debug facility' [patent_app_type] => new-utility [patent_app_number] => 09/748077 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5696 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20010007125.pdf [firstpage_image] =>[orig_patent_app_number] => 09748077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748077
Computer system with debug facility Dec 21, 2000 Abandoned
Array ( [id] => 706779 [patent_doc_number] => 07065636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Hardware loops and pipeline system using advanced generation of loop parameters' [patent_app_type] => utility [patent_app_number] => 09/745104 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3574 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/065/07065636.pdf [firstpage_image] =>[orig_patent_app_number] => 09745104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745104
Hardware loops and pipeline system using advanced generation of loop parameters Dec 19, 2000 Issued
Array ( [id] => 981651 [patent_doc_number] => 06931518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-16 [patent_title] => 'Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic' [patent_app_type] => utility [patent_app_number] => 09/724196 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1956 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/931/06931518.pdf [firstpage_image] =>[orig_patent_app_number] => 09724196 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724196
Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic Nov 27, 2000 Issued
09/723994 MAINTAINING A PE STATE OF A DATAPATH DURING CONDITIONAL PROCESSING IN A SINGLE INSTRUCTION MULTIPLE DATAPATH PROCESSOR ARCHITECTURE Nov 27, 2000 Abandoned
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