Search

Tekchand Saidha

Examiner (ID: 9531, Phone: (571)272-0940 , Office: P/1652 )

Most Active Art Unit
1652
Art Unit(s)
1814, 1652
Total Applications
2587
Issued Applications
1813
Pending Applications
368
Abandoned Applications
434

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15503465 [patent_doc_number] => 20200051921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING A BORON-CONTAINING INSULATING PATTERN [patent_app_type] => utility [patent_app_number] => 16/358212 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358212 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358212
Integrated circuit devices including a boron-containing insulating pattern Mar 18, 2019 Issued
Array ( [id] => 17270475 [patent_doc_number] => 11195905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Metal-oxide-semiconductor transistor and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/358556 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 3346 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358556
Metal-oxide-semiconductor transistor and method of fabricating the same Mar 18, 2019 Issued
Array ( [id] => 15873701 [patent_doc_number] => 20200144254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR (VFET) AND A FIN FIELD-EFFECT TRANSISTOR (FINFET) AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/358245 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358245 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358245
Integrated circuit devices including a vertical field-effect transistor (VFET) and a fin field-effect transistor (FinFET) and methods of forming the same Mar 18, 2019 Issued
Array ( [id] => 14573729 [patent_doc_number] => 20190214472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => MEMORY CELLS HAVING ELECTRICALLY CONDUCTIVE NANODOTS AND APPARATUS HAVING SUCH MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/357583 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16357583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/357583
Memory cells having electrically conductive nanodots and apparatus having such memory cells Mar 18, 2019 Issued
Array ( [id] => 16707905 [patent_doc_number] => 10957849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Magnetic tunnel junctions with coupling-pinning layer lattice matching [patent_app_type] => utility [patent_app_number] => 16/358475 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 14422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358475 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358475
Magnetic tunnel junctions with coupling-pinning layer lattice matching Mar 18, 2019 Issued
Array ( [id] => 16653601 [patent_doc_number] => 10930794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Self-aligned spacers for multi-gate devices and method of fabrication thereof [patent_app_type] => utility [patent_app_number] => 16/358314 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 64 [patent_no_of_words] => 11703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358314 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358314
Self-aligned spacers for multi-gate devices and method of fabrication thereof Mar 18, 2019 Issued
Array ( [id] => 16332317 [patent_doc_number] => 20200303283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => FLEXIBLE BASE DESIGN FOR CHIPSET HEAT SINK [patent_app_type] => utility [patent_app_number] => 16/358250 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358250 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358250
Flexible base design for chipset heat sink Mar 18, 2019 Issued
Array ( [id] => 14904497 [patent_doc_number] => 20190296014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => Circuit Arrangement, Redistribution Board, Module and Method of Fabricating a Half-Bridge Circuit [patent_app_type] => utility [patent_app_number] => 16/358309 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358309
Circuit arrangement, redistribution board, module and method of fabricating a half-bridge circuit Mar 18, 2019 Issued
Array ( [id] => 18387329 [patent_doc_number] => 11658122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => EMIB patch on glass laminate substrate [patent_app_type] => utility [patent_app_number] => 16/356442 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6647 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16356442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/356442
EMIB patch on glass laminate substrate Mar 17, 2019 Issued
Array ( [id] => 16699919 [patent_doc_number] => 10950527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/291872 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 8921 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291872 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291872
Semiconductor device and method for manufacturing the same Mar 3, 2019 Issued
Array ( [id] => 16301057 [patent_doc_number] => 20200286780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => FABRICATING VIAS WITH LOWER RESISTANCE [patent_app_type] => utility [patent_app_number] => 16/291463 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291463
Fabricating vias with lower resistance Mar 3, 2019 Issued
Array ( [id] => 16301182 [patent_doc_number] => 20200286905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => THREE-DIMENSIONAL DEVICE WITH BONDED STRUCTURES INCLUDING A SUPPORT DIE AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/291577 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 41770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291577
Three-dimensional device with bonded structures including a support die and methods of making the same Mar 3, 2019 Issued
Array ( [id] => 16410101 [patent_doc_number] => 10818666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Gate noble metal nanoparticles [patent_app_type] => utility [patent_app_number] => 16/291597 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7021 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291597
Gate noble metal nanoparticles Mar 3, 2019 Issued
Array ( [id] => 15717871 [patent_doc_number] => 20200105703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/291621 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291621
Fan-out semiconductor package Mar 3, 2019 Issued
Array ( [id] => 14509767 [patent_doc_number] => 20190198538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => Pixel Isolation Elements, Devices and Associated Methods [patent_app_type] => utility [patent_app_number] => 16/290740 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16290740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/290740
Pixel isolation elements, devices and associated methods Feb 28, 2019 Issued
Array ( [id] => 14509893 [patent_doc_number] => 20190198601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => CAPACITOR [patent_app_type] => utility [patent_app_number] => 16/286886 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286886 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286886
Capacitor Feb 26, 2019 Issued
Array ( [id] => 14510211 [patent_doc_number] => 20190198760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/287753 [patent_app_country] => US [patent_app_date] => 2019-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16287753 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/287753
Memory device Feb 26, 2019 Issued
Array ( [id] => 16448325 [patent_doc_number] => 10840256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Vertical memory devices and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/283141 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 86 [patent_figures_cnt] => 86 [patent_no_of_words] => 12833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283141
Vertical memory devices and methods of manufacturing the same Feb 21, 2019 Issued
Array ( [id] => 16016725 [patent_doc_number] => 20200183206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/462957 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16462957 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/462957
DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF Feb 20, 2019 Abandoned
Array ( [id] => 16414351 [patent_doc_number] => 10822226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Semiconductor package using a polymer substrate [patent_app_type] => utility [patent_app_number] => 16/255292 [patent_app_country] => US [patent_app_date] => 2019-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16255292 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/255292
Semiconductor package using a polymer substrate Jan 22, 2019 Issued
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