
Telly D. Green
Examiner (ID: 11748)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2809, 2898, 2822 |
| Total Applications | 1668 |
| Issued Applications | 1348 |
| Pending Applications | 113 |
| Abandoned Applications | 249 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17661100
[patent_doc_number] => 20220181565
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-09
[patent_title] => GATE ALL AROUND SEMICONDUCTOR STRUCTURE WITH DIFFUSION BREAK
[patent_app_type] => utility
[patent_app_number] => 17/680199
[patent_app_country] => US
[patent_app_date] => 2022-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10286
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680199
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/680199 | Gate all around semiconductor structure with diffusion break | Feb 23, 2022 | Issued |
Array
(
[id] => 18759802
[patent_doc_number] => 11810839
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-07
[patent_title] => Semiconductor package with die stacked on surface mounted devices
[patent_app_type] => utility
[patent_app_number] => 17/674697
[patent_app_country] => US
[patent_app_date] => 2022-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 6521
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674697
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/674697 | Semiconductor package with die stacked on surface mounted devices | Feb 16, 2022 | Issued |
Array
(
[id] => 18488507
[patent_doc_number] => 20230215855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/673749
[patent_app_country] => US
[patent_app_date] => 2022-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3125
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673749
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/673749 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME | Feb 15, 2022 | Pending |
Array
(
[id] => 18570634
[patent_doc_number] => 20230260971
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-17
[patent_title] => VERTICALLY STACKED FET WITH STRAINED CHANNEL
[patent_app_type] => utility
[patent_app_number] => 17/669788
[patent_app_country] => US
[patent_app_date] => 2022-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12076
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669788
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/669788 | Vertically stacked FET with strained channel | Feb 10, 2022 | Issued |
Array
(
[id] => 18580770
[patent_doc_number] => 11737319
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-22
[patent_title] => Display apparatus including a blocking layer and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/592658
[patent_app_country] => US
[patent_app_date] => 2022-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 8961
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592658
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/592658 | Display apparatus including a blocking layer and method of manufacturing the same | Feb 3, 2022 | Issued |
Array
(
[id] => 17615316
[patent_doc_number] => 20220157596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => Varying Temperature Anneal for Film and Structures Formed Thereby
[patent_app_type] => utility
[patent_app_number] => 17/591176
[patent_app_country] => US
[patent_app_date] => 2022-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7620
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591176
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/591176 | Varying temperature anneal for film and structures formed thereby | Feb 1, 2022 | Issued |
Array
(
[id] => 18112985
[patent_doc_number] => 20230005865
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-05
[patent_title] => THREE-DIMENSIONAL MEMORY DEVICES, SYSTEMS, AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/587656
[patent_app_country] => US
[patent_app_date] => 2022-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17743
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587656
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/587656 | THREE-DIMENSIONAL MEMORY DEVICES, SYSTEMS, AND METHODS FOR FORMING THE SAME | Jan 27, 2022 | Abandoned |
Array
(
[id] => 18533277
[patent_doc_number] => 20230238353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-27
[patent_title] => A METHOD OF FORMING A BONDED SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/585869
[patent_app_country] => US
[patent_app_date] => 2022-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6809
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585869
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/585869 | Method of forming a bonded semiconductor structure | Jan 26, 2022 | Issued |
Array
(
[id] => 19016379
[patent_doc_number] => 11923321
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-05
[patent_title] => Three-dimensional memory device including dielectric rails for warpage reduction and method of making the same
[patent_app_type] => utility
[patent_app_number] => 17/574182
[patent_app_country] => US
[patent_app_date] => 2022-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 38
[patent_no_of_words] => 12737
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574182
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/574182 | Three-dimensional memory device including dielectric rails for warpage reduction and method of making the same | Jan 11, 2022 | Issued |
Array
(
[id] => 17708715
[patent_doc_number] => 20220208723
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-30
[patent_title] => DIRECTLY BONDED STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 17/646361
[patent_app_country] => US
[patent_app_date] => 2021-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11269
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646361
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/646361 | DIRECTLY BONDED STRUCTURES | Dec 28, 2021 | Pending |
Array
(
[id] => 18646858
[patent_doc_number] => 11770950
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-26
[patent_title] => Borosilicate light extraction region
[patent_app_type] => utility
[patent_app_number] => 17/562500
[patent_app_country] => US
[patent_app_date] => 2021-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 9941
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562500
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/562500 | Borosilicate light extraction region | Dec 26, 2021 | Issued |
Array
(
[id] => 19294595
[patent_doc_number] => 12033959
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Dummy pattern structure for reducing dishing
[patent_app_type] => utility
[patent_app_number] => 17/546003
[patent_app_country] => US
[patent_app_date] => 2021-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 11882
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546003
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/546003 | Dummy pattern structure for reducing dishing | Dec 7, 2021 | Issued |
Array
(
[id] => 17855261
[patent_doc_number] => 20220285304
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-08
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/543617
[patent_app_country] => US
[patent_app_date] => 2021-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4247
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543617
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/543617 | Semiconductor package and method of manufacturing the same | Dec 5, 2021 | Issued |
Array
(
[id] => 17477485
[patent_doc_number] => 20220084989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONNECTING STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/537998
[patent_app_country] => US
[patent_app_date] => 2021-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11088
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537998
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/537998 | Method for fabricating semiconductor device with connecting structure | Nov 29, 2021 | Issued |
Array
(
[id] => 17886480
[patent_doc_number] => 20220301958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/535937
[patent_app_country] => US
[patent_app_date] => 2021-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535937
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/535937 | SEMICONDUCTOR PACKAGE | Nov 25, 2021 | Abandoned |
Array
(
[id] => 19029982
[patent_doc_number] => 11929348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-12
[patent_title] => Vertically mounted die groups
[patent_app_type] => utility
[patent_app_number] => 17/534395
[patent_app_country] => US
[patent_app_date] => 2021-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 13147
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534395
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/534395 | Vertically mounted die groups | Nov 22, 2021 | Issued |
Array
(
[id] => 19679423
[patent_doc_number] => 12191296
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => Method of producing a multi-chip assembly
[patent_app_type] => utility
[patent_app_number] => 17/520924
[patent_app_country] => US
[patent_app_date] => 2021-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 7683
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520924
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/520924 | Method of producing a multi-chip assembly | Nov 7, 2021 | Issued |
Array
(
[id] => 18371931
[patent_doc_number] => 11652113
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-16
[patent_title] => Image sensor
[patent_app_type] => utility
[patent_app_number] => 17/519701
[patent_app_country] => US
[patent_app_date] => 2021-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 9518
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519701
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/519701 | Image sensor | Nov 4, 2021 | Issued |
Array
(
[id] => 17855165
[patent_doc_number] => 20220285208
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-08
[patent_title] => SEMICONDUCTOR CHIP STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/453504
[patent_app_country] => US
[patent_app_date] => 2021-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14408
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453504
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/453504 | Semiconductor chip structure | Nov 3, 2021 | Issued |
Array
(
[id] => 17676621
[patent_doc_number] => 20220189788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-16
[patent_title] => OPTICAL SENSOR PACKAGE AND METHOD OF MAKING AN OPTICAL SENSOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 17/513122
[patent_app_country] => US
[patent_app_date] => 2021-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4132
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17513122
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/513122 | Optical sensor package and method of making an optical sensor package | Oct 27, 2021 | Issued |