| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2689292
[patent_doc_number] => 05067108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-19
[patent_title] => 'Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate'
[patent_app_type] => 1
[patent_app_number] => 7/467918
[patent_app_country] => US
[patent_app_date] => 1990-01-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/067/05067108.pdf
[firstpage_image] =>[orig_patent_app_number] => 467918
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/467918 | Single transistor non-volatile electrically alterable semiconductor memory device with a re-crystallized floating gate | Jan 21, 1990 | Issued |
Array
(
[id] => 2688935
[patent_doc_number] => 05005158
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-02
[patent_title] => 'Redundancy for serial memory'
[patent_app_type] => 1
[patent_app_number] => 7/464219
[patent_app_country] => US
[patent_app_date] => 1990-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/005/05005158.pdf
[firstpage_image] =>[orig_patent_app_number] => 464219
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/464219 | Redundancy for serial memory | Jan 11, 1990 | Issued |
| 07/462119 | SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY CIRCUITS | Jan 9, 1990 | Abandoned |
| 07/461225 | APPARATUS FOR MAINTAINING CONSISTENCY IN A MULTIPROCESSOR COMPUTER SYSTEM USING VIRTUAL CACHING | Jan 4, 1990 | Abandoned |
Array
(
[id] => 2889925
[patent_doc_number] => 05109361
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Electrically page erasable and programmable read only memory'
[patent_app_type] => 1
[patent_app_number] => 7/460737
[patent_app_country] => US
[patent_app_date] => 1990-01-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/109/05109361.pdf
[firstpage_image] =>[orig_patent_app_number] => 460737
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/460737 | Electrically page erasable and programmable read only memory | Jan 3, 1990 | Issued |
Array
(
[id] => 2776494
[patent_doc_number] => 05036495
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-30
[patent_title] => 'Multiple mode-set for IC chip'
[patent_app_type] => 1
[patent_app_number] => 7/469880
[patent_app_country] => US
[patent_app_date] => 1989-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2583
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[pdf_file] => patents/05/036/05036495.pdf
[firstpage_image] =>[orig_patent_app_number] => 469880
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/469880 | Multiple mode-set for IC chip | Dec 27, 1989 | Issued |
| 07/456869 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PREVENTING READ ERROR CAUSED BY OVERERASE STATE | Dec 26, 1989 | Abandoned |
| 07/457470 | INPUT SIGNAL REDRIVER FOR SEMICONDUCTOR MODULES | Dec 26, 1989 | Abandoned |
| 07/455989 | DYNAMIC SEMICONDUCTOR MEMORY DEVICE HAVING A MULTI-LEVEL MEMORY CELL WITH A LARGER READ-OUT MARGIN | Dec 21, 1989 | Abandoned |
Array
(
[id] => 2734834
[patent_doc_number] => 05058063
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-15
[patent_title] => 'Nonvolatile semiconductor memory device incorporating level shifting circuits'
[patent_app_type] => 1
[patent_app_number] => 7/454740
[patent_app_country] => US
[patent_app_date] => 1989-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] => patents/05/058/05058063.pdf
[firstpage_image] =>[orig_patent_app_number] => 454740
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/454740 | Nonvolatile semiconductor memory device incorporating level shifting circuits | Dec 20, 1989 | Issued |
Array
(
[id] => 2877733
[patent_doc_number] => 05097445
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-17
[patent_title] => 'Semiconductor integrated circuit with selective read and write inhibiting'
[patent_app_type] => 1
[patent_app_number] => 7/450809
[patent_app_country] => US
[patent_app_date] => 1989-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/05/097/05097445.pdf
[firstpage_image] =>[orig_patent_app_number] => 450809
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/450809 | Semiconductor integrated circuit with selective read and write inhibiting | Dec 13, 1989 | Issued |
Array
(
[id] => 2854008
[patent_doc_number] => 05138575
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-11
[patent_title] => 'Electricaly erasable and programmable read only memory with a discharge device'
[patent_app_type] => 1
[patent_app_number] => 7/448470
[patent_app_country] => US
[patent_app_date] => 1989-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4885
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/138/05138575.pdf
[firstpage_image] =>[orig_patent_app_number] => 448470
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/448470 | Electricaly erasable and programmable read only memory with a discharge device | Dec 10, 1989 | Issued |
Array
(
[id] => 3004215
[patent_doc_number] => 05347642
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-13
[patent_title] => 'Cache memory management unit'
[patent_app_type] => 1
[patent_app_number] => 7/443996
[patent_app_country] => US
[patent_app_date] => 1989-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/347/05347642.pdf
[firstpage_image] =>[orig_patent_app_number] => 443996
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/443996 | Cache memory management unit | Nov 29, 1989 | Issued |
Array
(
[id] => 2742266
[patent_doc_number] => 05040144
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-13
[patent_title] => 'Integrated circuit with improved power supply distribution'
[patent_app_type] => 1
[patent_app_number] => 7/442268
[patent_app_country] => US
[patent_app_date] => 1989-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/040/05040144.pdf
[firstpage_image] =>[orig_patent_app_number] => 442268
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/442268 | Integrated circuit with improved power supply distribution | Nov 27, 1989 | Issued |
Array
(
[id] => 3064753
[patent_doc_number] => 05307470
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-26
[patent_title] => 'Microcomputer having EEPROM provided with detector for detecting data write request issued before data write operation responsive to preceding data write request is completed'
[patent_app_type] => 1
[patent_app_number] => 7/441739
[patent_app_country] => US
[patent_app_date] => 1989-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3428
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[pdf_file] => patents/05/307/05307470.pdf
[firstpage_image] =>[orig_patent_app_number] => 441739
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/441739 | Microcomputer having EEPROM provided with detector for detecting data write request issued before data write operation responsive to preceding data write request is completed | Nov 26, 1989 | Issued |
| 07/441588 | SEMICONDUCTOR MEMORY DEVICE AND DATA TRANSFERRING STRUCTURE AND METHOD THEREIN | Nov 26, 1989 | Abandoned |
| 07/440826 | ARCHITECTURE AND CONFIGURING METHOD FOR A COMPUTER EXPANSION BOARD | Nov 23, 1989 | Abandoned |
| 07/440338 | SEMICONDUCTOR MEMORY DEVICE HAVING AN AUTOMATICALLY ACTIVATED VERIFY FUNCTION CAPABILITY | Nov 21, 1989 | Abandoned |
| 07/437874 | SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF MEMORY ARRAYS WITH IMPROVED PERIPHERAL CIRCUIT LOCATION AND INTERCONNECTION ARRANGEMENT | Nov 16, 1989 | Abandoned |
Array
(
[id] => 2877638
[patent_doc_number] => 05097440
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-17
[patent_title] => 'Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement'
[patent_app_type] => 1
[patent_app_number] => 7/437867
[patent_app_country] => US
[patent_app_date] => 1989-11-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/097/05097440.pdf
[firstpage_image] =>[orig_patent_app_number] => 437867
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/437867 | Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement | Nov 16, 1989 | Issued |
