| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2753564
[patent_doc_number] => 05029140
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-02
[patent_title] => 'Dynamic memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/437378
[patent_app_country] => US
[patent_app_date] => 1989-11-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/029/05029140.pdf
[firstpage_image] =>[orig_patent_app_number] => 437378
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/437378 | Dynamic memory cell | Nov 14, 1989 | Issued |
Array
(
[id] => 2823651
[patent_doc_number] => 05079743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-07
[patent_title] => 'Circuit for applying selected voltages to dynamic random access memory'
[patent_app_type] => 1
[patent_app_number] => 7/436587
[patent_app_country] => US
[patent_app_date] => 1989-11-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/079/05079743.pdf
[firstpage_image] =>[orig_patent_app_number] => 436587
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/436587 | Circuit for applying selected voltages to dynamic random access memory | Nov 14, 1989 | Issued |
| 07/432837 | DYNAMIC-TYPE SEMICONDUCTOR MEMORY DEVICE OPERABLE IN TEST MODE AND METHOD OF TESTING FUNCTIONS THEREOF | Nov 6, 1989 | Abandoned |
Array
(
[id] => 2776349
[patent_doc_number] => 05036487
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-30
[patent_title] => 'CMOS-RAM memory in a gate array arrangement'
[patent_app_type] => 1
[patent_app_number] => 7/449839
[patent_app_country] => US
[patent_app_date] => 1989-11-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/036/05036487.pdf
[firstpage_image] =>[orig_patent_app_number] => 449839
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/449839 | CMOS-RAM memory in a gate array arrangement | Nov 5, 1989 | Issued |
Array
(
[id] => 2759961
[patent_doc_number] => 05022010
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-04
[patent_title] => 'Word decoder for a memory array'
[patent_app_type] => 1
[patent_app_number] => 7/428793
[patent_app_country] => US
[patent_app_date] => 1989-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6909
[patent_no_of_claims] => 5
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[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/022/05022010.pdf
[firstpage_image] =>[orig_patent_app_number] => 428793
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/428793 | Word decoder for a memory array | Oct 29, 1989 | Issued |
| 07/428794 | BIT DECODE SCHEME FOR MEMORY ARRAYS | Oct 29, 1989 | Abandoned |
Array
(
[id] => 2689345
[patent_doc_number] => 05067111
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-19
[patent_title] => 'Semiconductor memory device having a majority logic for determining data to be read out'
[patent_app_type] => 1
[patent_app_number] => 7/426803
[patent_app_country] => US
[patent_app_date] => 1989-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] => patents/05/067/05067111.pdf
[firstpage_image] =>[orig_patent_app_number] => 426803
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/426803 | Semiconductor memory device having a majority logic for determining data to be read out | Oct 25, 1989 | Issued |
Array
(
[id] => 2589466
[patent_doc_number] => 04974205
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-11-27
[patent_title] => 'Josephson memory and read/write circuit'
[patent_app_type] => 1
[patent_app_number] => 7/426074
[patent_app_country] => US
[patent_app_date] => 1989-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/04/974/04974205.pdf
[firstpage_image] =>[orig_patent_app_number] => 426074
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/426074 | Josephson memory and read/write circuit | Oct 22, 1989 | Issued |
| 07/424904 | SEMICONDUCTOR MEMORY DEVICE WITH AN IMPROVED REFRESHING ARRANGEMENT | Oct 17, 1989 | Abandoned |
Array
(
[id] => 2889875
[patent_doc_number] => 05109358
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-28
[patent_title] => 'Optical flip-flop circuit'
[patent_app_type] => 1
[patent_app_number] => 7/423203
[patent_app_country] => US
[patent_app_date] => 1989-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2737
[patent_no_of_claims] => 8
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[patent_words_short_claim] => 39
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/109/05109358.pdf
[firstpage_image] =>[orig_patent_app_number] => 423203
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/423203 | Optical flip-flop circuit | Oct 16, 1989 | Issued |
| 07/421482 | SYSTEM AND METHOD FOR EXECUTING PANEL ACTIONS FROM PROCEDURES | Oct 12, 1989 | Abandoned |
| 07/420964 | DOUBLE STAGE BIPOLAR SENSE AMPLIFIER FOR BICMOS SRAMS WITH A COMMON BASE AMPLIFIER IN THE FINAL STAGE | Oct 12, 1989 | Abandoned |
| 07/420851 | CACHE MEMORY CONTROLLER WITH BURST AND HIDDEN REFRESH | Oct 12, 1989 | Abandoned |
| 07/419399 | SEMICONDUCTOR DEVICE HAVING REDUNDANCY CIRCUIT | Oct 9, 1989 | Abandoned |
| 07/404712 | ACCESS AUTHORIZATION TABLE FOR MULTI-PROCESSOR CACHES | Sep 7, 1989 | Abandoned |
Array
(
[id] => 2847743
[patent_doc_number] => 05161122
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-03
[patent_title] => 'Register write bit protection apparatus and method'
[patent_app_type] => 1
[patent_app_number] => 7/387553
[patent_app_country] => US
[patent_app_date] => 1989-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1913
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[pdf_file] => patents/05/161/05161122.pdf
[firstpage_image] =>[orig_patent_app_number] => 387553
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/387553 | Register write bit protection apparatus and method | Jul 27, 1989 | Issued |
Array
(
[id] => 2960479
[patent_doc_number] => 05262984
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-16
[patent_title] => 'Non-volatile memory device capable of storing multi-state data'
[patent_app_type] => 1
[patent_app_number] => 7/386484
[patent_app_country] => US
[patent_app_date] => 1989-07-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/262/05262984.pdf
[firstpage_image] =>[orig_patent_app_number] => 386484
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/386484 | Non-volatile memory device capable of storing multi-state data | Jul 27, 1989 | Issued |
Array
(
[id] => 2680043
[patent_doc_number] => 05034921
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-23
[patent_title] => 'High speed optical memory circuit'
[patent_app_type] => 1
[patent_app_number] => 7/375983
[patent_app_country] => US
[patent_app_date] => 1989-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[pdf_file] => patents/05/034/05034921.pdf
[firstpage_image] =>[orig_patent_app_number] => 375983
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/375983 | High speed optical memory circuit | Jul 5, 1989 | Issued |
Array
(
[id] => 2924983
[patent_doc_number] => 05179538
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-12
[patent_title] => 'Memory system including CMOS memory cells and bipolar sensing circuit'
[patent_app_type] => 1
[patent_app_number] => 7/373948
[patent_app_country] => US
[patent_app_date] => 1989-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
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[pdf_file] => patents/05/179/05179538.pdf
[firstpage_image] =>[orig_patent_app_number] => 373948
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/373948 | Memory system including CMOS memory cells and bipolar sensing circuit | Jun 29, 1989 | Issued |
| 07/372777 | ROM CARD | Jun 28, 1989 | Abandoned |