| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 2757222
[patent_doc_number] => 05029330
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-02
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/364458
[patent_app_country] => US
[patent_app_date] => 1989-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 14064
[patent_no_of_claims] => 26
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/029/05029330.pdf
[firstpage_image] =>[orig_patent_app_number] => 364458
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/364458 | Semiconductor memory device | Jun 11, 1989 | Issued |
Array
(
[id] => 2719012
[patent_doc_number] => 05042011
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-20
[patent_title] => 'Sense amplifier pulldown device with tailored edge input'
[patent_app_type] => 1
[patent_app_number] => 7/355299
[patent_app_country] => US
[patent_app_date] => 1989-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 1330
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/042/05042011.pdf
[firstpage_image] =>[orig_patent_app_number] => 355299
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/355299 | Sense amplifier pulldown device with tailored edge input | May 21, 1989 | Issued |
Array
(
[id] => 2717055
[patent_doc_number] => 04982371
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-01-01
[patent_title] => 'Compact electronic module having a RAM device'
[patent_app_type] => 1
[patent_app_number] => 7/351759
[patent_app_country] => US
[patent_app_date] => 1989-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 48
[patent_no_of_words] => 21496
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/982/04982371.pdf
[firstpage_image] =>[orig_patent_app_number] => 351759
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/351759 | Compact electronic module having a RAM device | May 14, 1989 | Issued |
Array
(
[id] => 2905049
[patent_doc_number] => 05210846
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-11
[patent_title] => 'One-wire bus architecture'
[patent_app_type] => 1
[patent_app_number] => 7/352581
[patent_app_country] => US
[patent_app_date] => 1989-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 48
[patent_no_of_words] => 22181
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/210/05210846.pdf
[firstpage_image] =>[orig_patent_app_number] => 352581
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/352581 | One-wire bus architecture | May 14, 1989 | Issued |
Array
(
[id] => 2815538
[patent_doc_number] => 05148395
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-15
[patent_title] => 'Dual EEPROM cell with current mirror differential read'
[patent_app_type] => 1
[patent_app_number] => 7/343974
[patent_app_country] => US
[patent_app_date] => 1989-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3061
[patent_no_of_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/148/05148395.pdf
[firstpage_image] =>[orig_patent_app_number] => 343974
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/343974 | Dual EEPROM cell with current mirror differential read | Apr 25, 1989 | Issued |
Array
(
[id] => 2759729
[patent_doc_number] => 05021998
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-04
[patent_title] => 'Semiconductor memory device with low-house pads for electron beam test'
[patent_app_type] => 1
[patent_app_number] => 7/339843
[patent_app_country] => US
[patent_app_date] => 1989-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6220
[patent_no_of_claims] => 15
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/021/05021998.pdf
[firstpage_image] =>[orig_patent_app_number] => 339843
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/339843 | Semiconductor memory device with low-house pads for electron beam test | Apr 17, 1989 | Issued |
| 07/337703 | SERIAL ACCESS SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREFOR | Apr 12, 1989 | Abandoned |
Array
(
[id] => 2719536
[patent_doc_number] => 05018104
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-21
[patent_title] => 'Redundant circuit incorporated in semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/337003
[patent_app_country] => US
[patent_app_date] => 1989-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3997
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/018/05018104.pdf
[firstpage_image] =>[orig_patent_app_number] => 337003
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/337003 | Redundant circuit incorporated in semiconductor memory device | Apr 11, 1989 | Issued |
| 07/332963 | SUPERCONDUCTING MAGNETIC MEMORY | Apr 3, 1989 | Abandoned |
Array
(
[id] => 2705991
[patent_doc_number] => 04991138
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-02-05
[patent_title] => 'High speed memory cell with multiple port capability'
[patent_app_type] => 1
[patent_app_number] => 7/331989
[patent_app_country] => US
[patent_app_date] => 1989-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3088
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/991/04991138.pdf
[firstpage_image] =>[orig_patent_app_number] => 331989
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/331989 | High speed memory cell with multiple port capability | Apr 2, 1989 | Issued |
| 07/332870 | METHOD FOR MANAGING AN LRU PRIORITIZED CACHE | Apr 2, 1989 | Abandoned |
Array
(
[id] => 2725467
[patent_doc_number] => 05054002
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-01
[patent_title] => 'Memory unit with compensating delay circuit corresponding to a decoder delay'
[patent_app_type] => 1
[patent_app_number] => 7/331784
[patent_app_country] => US
[patent_app_date] => 1989-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3543
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 488
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/054/05054002.pdf
[firstpage_image] =>[orig_patent_app_number] => 331784
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/331784 | Memory unit with compensating delay circuit corresponding to a decoder delay | Apr 2, 1989 | Issued |
| 07/331684 | BIT LINE DISCHARGE AND SENSE CIRCUIT | Mar 29, 1989 | Abandoned |
| 07/328564 | METHOD OF DRIVING DEVICE HAVING MIM STRUCTURE | Mar 23, 1989 | Abandoned |
| 07/328413 | SUPERCONDUCTING MEMORY CIRCUIT | Mar 23, 1989 | Abandoned |
Array
(
[id] => 2753577
[patent_doc_number] => 05029141
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-02
[patent_title] => 'Dynamic semiconductor memory with block decoding'
[patent_app_type] => 1
[patent_app_number] => 7/322843
[patent_app_country] => US
[patent_app_date] => 1989-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3747
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 297
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/029/05029141.pdf
[firstpage_image] =>[orig_patent_app_number] => 322843
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/322843 | Dynamic semiconductor memory with block decoding | Mar 13, 1989 | Issued |
Array
(
[id] => 2680008
[patent_doc_number] => 05047989
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-10
[patent_title] => 'Chapter mode selection apparatus for MOS memory'
[patent_app_type] => 1
[patent_app_number] => 7/321909
[patent_app_country] => US
[patent_app_date] => 1989-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 4198
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/047/05047989.pdf
[firstpage_image] =>[orig_patent_app_number] => 321909
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/321909 | Chapter mode selection apparatus for MOS memory | Mar 9, 1989 | Issued |
| 07/318234 | CMOS RAM HAVING A COMPLEMENTARY CHANNEL SENSE AMPLIFIER | Mar 2, 1989 | Abandoned |
| 07/317483 | SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED REDUNDANT CIRCUIT | Feb 28, 1989 | Abandoned |
Array
(
[id] => 2758491
[patent_doc_number] => 05031142
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Reset circuit for redundant memory using CAM cells'
[patent_app_type] => 1
[patent_app_number] => 7/309384
[patent_app_country] => US
[patent_app_date] => 1989-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3617
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/031/05031142.pdf
[firstpage_image] =>[orig_patent_app_number] => 309384
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/309384 | Reset circuit for redundant memory using CAM cells | Feb 9, 1989 | Issued |