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Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2567884 [patent_doc_number] => 04817058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-28 [patent_title] => 'Multiple input/output read/write memory having a multiple-cycle write mask' [patent_app_type] => 1 [patent_app_number] => 7/053200 [patent_app_country] => US [patent_app_date] => 1987-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 10401 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/817/04817058.pdf [firstpage_image] =>[orig_patent_app_number] => 053200 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/053200
Multiple input/output read/write memory having a multiple-cycle write mask May 20, 1987 Issued
Array ( [id] => 2985248 [patent_doc_number] => 05208772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-04 [patent_title] => 'Gate EEPROM cell' [patent_app_type] => 1 [patent_app_number] => 6/869469 [patent_app_country] => US [patent_app_date] => 1986-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3547 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/208/05208772.pdf [firstpage_image] =>[orig_patent_app_number] => 869469 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/869469
Gate EEPROM cell May 27, 1986 Issued
Array ( [id] => 2397775 [patent_doc_number] => 04794569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-27 [patent_title] => 'Semiconductor memory having a barrier transistor between a bit line and a sensing amplifier' [patent_app_type] => 1 [patent_app_number] => 6/863190 [patent_app_country] => US [patent_app_date] => 1986-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2194 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/794/04794569.pdf [firstpage_image] =>[orig_patent_app_number] => 863190 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/863190
Semiconductor memory having a barrier transistor between a bit line and a sensing amplifier May 13, 1986 Issued
Array ( [id] => 2692085 [patent_doc_number] => 05046046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-03 [patent_title] => 'Redundancy CAM using word line from memory' [patent_app_type] => 1 [patent_app_number] => 7/321904 [patent_app_country] => US [patent_app_date] => 1978-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3645 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/046/05046046.pdf [firstpage_image] =>[orig_patent_app_number] => 321904 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/321904
Redundancy CAM using word line from memory Mar 9, 1978 Issued
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