Search

Telly D. Green

Examiner (ID: 11748)

Most Active Art Unit
2822
Art Unit(s)
2809, 2898, 2822
Total Applications
1668
Issued Applications
1348
Pending Applications
113
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16372393 [patent_doc_number] => 10804159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Minimize middle-of-line contact line shorts [patent_app_type] => utility [patent_app_number] => 16/657516 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 4491 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657516 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657516
Minimize middle-of-line contact line shorts Oct 17, 2019 Issued
Array ( [id] => 15503417 [patent_doc_number] => 20200051897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/655843 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655843 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655843
SEMICONDUCTOR PACKAGE Oct 16, 2019 Abandoned
Array ( [id] => 15462169 [patent_doc_number] => 20200043909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => Method and Structure of Three-Dimensional Chip Stacking [patent_app_type] => utility [patent_app_number] => 16/599707 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599707 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599707
Method and structure of three-dimensional chip stacking Oct 10, 2019 Issued
Array ( [id] => 17210660 [patent_doc_number] => 11171036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Preventing dielectric void over trench isolation region [patent_app_type] => utility [patent_app_number] => 16/596814 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4139 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596814
Preventing dielectric void over trench isolation region Oct 8, 2019 Issued
Array ( [id] => 15969607 [patent_doc_number] => 20200168555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => Semiconductor Device with Multi-Layer Dielectric and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/597205 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597205 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597205
Semiconductor device with multi-layer dielectric Oct 8, 2019 Issued
Array ( [id] => 17848134 [patent_doc_number] => 11437521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Methods of forming a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/596487 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 14011 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596487 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596487
Methods of forming a semiconductor device Oct 7, 2019 Issued
Array ( [id] => 15768413 [patent_doc_number] => 20200115224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => MEMS DEVICE HAVING A RUGGED PACKAGE AND FABRICATION PROCESS THEREOF [patent_app_type] => utility [patent_app_number] => 16/596317 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596317 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596317
MEMS DEVICE HAVING A RUGGED PACKAGE AND FABRICATION PROCESS THEREOF Oct 7, 2019 Abandoned
Array ( [id] => 16774149 [patent_doc_number] => 10985273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile [patent_app_type] => utility [patent_app_number] => 16/589614 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589614
Vertical field-effect transistor including a fin having sidewalls with a tapered bottom profile Sep 30, 2019 Issued
Array ( [id] => 17107613 [patent_doc_number] => 11127841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions [patent_app_type] => utility [patent_app_number] => 16/589936 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 10535 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589936 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589936
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions Sep 30, 2019 Issued
Array ( [id] => 15414793 [patent_doc_number] => 20200027719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => Varying Temperature Anneal for Film and Structures Formed Thereby [patent_app_type] => utility [patent_app_number] => 16/587239 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587239 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587239
Varying temperature anneal for film and structures formed thereby Sep 29, 2019 Issued
Array ( [id] => 15369769 [patent_doc_number] => 20200020649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => Cavity based feature on chip carrier [patent_app_type] => utility [patent_app_number] => 16/578710 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578710
Cavity based feature on chip carrier Sep 22, 2019 Abandoned
Array ( [id] => 16774100 [patent_doc_number] => 10985223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Organic light emitting display device [patent_app_type] => utility [patent_app_number] => 16/577891 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 18938 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577891 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577891
Organic light emitting display device Sep 19, 2019 Issued
Array ( [id] => 15351781 [patent_doc_number] => 20200013782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING ENLARGED CONTACT HOLE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/571415 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16571415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/571415
Semiconductor devices including enlarged contact hole and methods of forming the same Sep 15, 2019 Issued
Array ( [id] => 18767053 [patent_doc_number] => 11817467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Solid-state imaging device and electronic device [patent_app_type] => utility [patent_app_number] => 17/283147 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 12143 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17283147 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/283147
Solid-state imaging device and electronic device Sep 11, 2019 Issued
Array ( [id] => 17716875 [patent_doc_number] => 11380876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Display substrate, method for manufacturing the same and display device [patent_app_type] => utility [patent_app_number] => 16/563214 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3859 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563214
Display substrate, method for manufacturing the same and display device Sep 5, 2019 Issued
Array ( [id] => 15300063 [patent_doc_number] => 20190393167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => APPARATUSES AND METHODS FOR SHIELDED MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/563691 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563691
Apparatuses and methods for shielded memory architecture Sep 5, 2019 Issued
Array ( [id] => 15300341 [patent_doc_number] => 20190393306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => FORMATION OF SELF-LIMITED INNER SPACER FOR GATE-ALL-AROUND NANOSHEET FET [patent_app_type] => utility [patent_app_number] => 16/561983 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561983 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561983
Formation of self-limited inner spacer for gate-all-around nanosheet FET Sep 4, 2019 Issued
Array ( [id] => 15939535 [patent_doc_number] => 20200161401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => DISPLAY SUBSTRATE, METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/560281 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560281
DISPLAY SUBSTRATE, METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE Sep 3, 2019 Abandoned
Array ( [id] => 16973704 [patent_doc_number] => 11069686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Techniques for enhancing vertical gate-all-around FET performance [patent_app_type] => utility [patent_app_number] => 16/560679 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6834 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560679 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560679
Techniques for enhancing vertical gate-all-around FET performance Sep 3, 2019 Issued
Array ( [id] => 15300253 [patent_doc_number] => 20190393262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => IMAGE SENSOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/560992 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560992
Image sensor structure Sep 3, 2019 Issued
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