
Telly D. Green
Examiner (ID: 11748)
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2809, 2898, 2822 |
| Total Applications | 1668 |
| Issued Applications | 1348 |
| Pending Applications | 113 |
| Abandoned Applications | 249 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16433069
[patent_doc_number] => 10833168
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-11-10
[patent_title] => Complementary metal-oxide-semiconductor (CMOS) nanosheet devices with epitaxial source/drains and replacement metal gate structures
[patent_app_type] => utility
[patent_app_number] => 16/297145
[patent_app_country] => US
[patent_app_date] => 2019-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 24
[patent_no_of_words] => 8277
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16297145
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/297145 | Complementary metal-oxide-semiconductor (CMOS) nanosheet devices with epitaxial source/drains and replacement metal gate structures | Mar 7, 2019 | Issued |
Array
(
[id] => 14875313
[patent_doc_number] => 20190287898
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-19
[patent_title] => METHODS AND APPARATUS FOR EMBEDDED ANTIFUSES
[patent_app_type] => utility
[patent_app_number] => 16/296929
[patent_app_country] => US
[patent_app_date] => 2019-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3227
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16296929
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/296929 | METHODS AND APPARATUS FOR EMBEDDED ANTIFUSES | Mar 7, 2019 | Abandoned |
Array
(
[id] => 15687919
[patent_doc_number] => 20200098623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => Contacts and Interconnect Structures in Field-Effect Transistors
[patent_app_type] => utility
[patent_app_number] => 16/297117
[patent_app_country] => US
[patent_app_date] => 2019-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11637
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16297117
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/297117 | Contacts and interconnect structures in field-effect transistors | Mar 7, 2019 | Issued |
Array
(
[id] => 17410506
[patent_doc_number] => 11251406
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Borosilicate light extraction region
[patent_app_type] => utility
[patent_app_number] => 16/295566
[patent_app_country] => US
[patent_app_date] => 2019-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 9908
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16295566
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/295566 | Borosilicate light extraction region | Mar 6, 2019 | Issued |
Array
(
[id] => 16324243
[patent_doc_number] => 10784215
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Millimeter wave integrated circuit and system with a low loss package transition
[patent_app_type] => utility
[patent_app_number] => 16/266122
[patent_app_country] => US
[patent_app_date] => 2019-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 3187
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266122
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/266122 | Millimeter wave integrated circuit and system with a low loss package transition | Feb 3, 2019 | Issued |
Array
(
[id] => 15657673
[patent_doc_number] => 20200091367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-19
[patent_title] => PHOTOCOUPLER
[patent_app_type] => utility
[patent_app_number] => 16/266138
[patent_app_country] => US
[patent_app_date] => 2019-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3359
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 359
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266138
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/266138 | PHOTOCOUPLER | Feb 3, 2019 | Abandoned |
Array
(
[id] => 14746351
[patent_doc_number] => 20190256349
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-22
[patent_title] => PHYSICAL QUANTITY SENSOR AND SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/266159
[patent_app_country] => US
[patent_app_date] => 2019-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6847
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266159
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/266159 | PHYSICAL QUANTITY SENSOR AND SEMICONDUCTOR DEVICE | Feb 3, 2019 | Abandoned |
Array
(
[id] => 15503615
[patent_doc_number] => 20200051996
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-13
[patent_title] => VERTICAL MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/266127
[patent_app_country] => US
[patent_app_date] => 2019-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11723
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16266127
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/266127 | Vertical memory devices | Feb 3, 2019 | Issued |
Array
(
[id] => 15823117
[patent_doc_number] => 10636754
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-28
[patent_title] => Semiconductor chip and method for forming a chip pad
[patent_app_type] => utility
[patent_app_number] => 16/262530
[patent_app_country] => US
[patent_app_date] => 2019-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6280
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262530
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/262530 | Semiconductor chip and method for forming a chip pad | Jan 29, 2019 | Issued |
Array
(
[id] => 15841115
[patent_doc_number] => 20200135840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-30
[patent_title] => SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING
[patent_app_type] => utility
[patent_app_number] => 16/253939
[patent_app_country] => US
[patent_app_date] => 2019-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8115
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16253939
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/253939 | Semiconductor arrangement and method of making | Jan 21, 2019 | Issued |
Array
(
[id] => 14284941
[patent_doc_number] => 20190139755
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => METHODS OF FORMING STAIRCASE-SHAPED CONNECTION STRUCTURES OF THREE-DIMENSIONAL SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/240216
[patent_app_country] => US
[patent_app_date] => 2019-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9044
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16240216
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/240216 | Methods of forming staircase-shaped connection structures of three-dimensional semiconductor devices | Jan 3, 2019 | Issued |
Array
(
[id] => 14969151
[patent_doc_number] => 20190312054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-10
[patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/239130
[patent_app_country] => US
[patent_app_date] => 2019-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13036
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239130
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/239130 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE | Jan 2, 2019 | Abandoned |
Array
(
[id] => 17803205
[patent_doc_number] => 11417516
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-16
[patent_title] => Dielectric layer and a semiconductor memory device including the dielectric layer as a capacitor dielectric layer
[patent_app_type] => utility
[patent_app_number] => 16/225432
[patent_app_country] => US
[patent_app_date] => 2018-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 5857
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16225432
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/225432 | Dielectric layer and a semiconductor memory device including the dielectric layer as a capacitor dielectric layer | Dec 18, 2018 | Issued |
Array
(
[id] => 14475659
[patent_doc_number] => 20190189477
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-20
[patent_title] => OPTOELECTRONIC SEMICONDUCTOR STAMP AND MANUFACTURING METHOD THEREOF, AND OPTOELECTRONIC SEMICONDUCTOR
[patent_app_type] => utility
[patent_app_number] => 16/224277
[patent_app_country] => US
[patent_app_date] => 2018-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7048
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16224277
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/224277 | OPTOELECTRONIC SEMICONDUCTOR STAMP AND MANUFACTURING METHOD THEREOF, AND OPTOELECTRONIC SEMICONDUCTOR | Dec 17, 2018 | Abandoned |
Array
(
[id] => 14285297
[patent_doc_number] => 20190139933
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => 3D Chip-on-Wafer-on-Substrate Structure with Via Last Process
[patent_app_type] => utility
[patent_app_number] => 16/221831
[patent_app_country] => US
[patent_app_date] => 2018-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8083
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221831
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/221831 | 3D Chip-on-wager-on-substrate structure with via last process | Dec 16, 2018 | Issued |
Array
(
[id] => 15688131
[patent_doc_number] => 20200098729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-26
[patent_title] => STACKING OF THREE-DIMENSIONAL CIRCUITS INCLUDING THROUGH-SILICON-VIAS
[patent_app_type] => utility
[patent_app_number] => 16/222460
[patent_app_country] => US
[patent_app_date] => 2018-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3836
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222460
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/222460 | Stacking of three-dimensional circuits including through-silicon-vias | Dec 16, 2018 | Issued |
Array
(
[id] => 16865914
[patent_doc_number] => 11024667
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Light-emitting device
[patent_app_type] => utility
[patent_app_number] => 16/222571
[patent_app_country] => US
[patent_app_date] => 2018-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 7978
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 329
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222571
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/222571 | Light-emitting device | Dec 16, 2018 | Issued |
Array
(
[id] => 14414207
[patent_doc_number] => 20190172947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-06
[patent_title] => THIN FILM TRANSISTORS WITH EPITAXIAL SOURCE/DRAIN AND DRAIN FIELD RELIEF
[patent_app_type] => utility
[patent_app_number] => 16/217701
[patent_app_country] => US
[patent_app_date] => 2018-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9859
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217701
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/217701 | Thin film transistors with epitaxial source/drain and drain field relief | Dec 11, 2018 | Issued |
Array
(
[id] => 17078233
[patent_doc_number] => 11114649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-07
[patent_title] => Light-emitting display device
[patent_app_type] => utility
[patent_app_number] => 16/197271
[patent_app_country] => US
[patent_app_date] => 2018-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 10339
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197271
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/197271 | Light-emitting display device | Nov 19, 2018 | Issued |
Array
(
[id] => 14050171
[patent_doc_number] => 20190081193
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-14
[patent_title] => NITRIDE UV LIGHT SENSORS ON SILICON SUBSTRATES
[patent_app_type] => utility
[patent_app_number] => 16/184621
[patent_app_country] => US
[patent_app_date] => 2018-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2360
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184621
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/184621 | NITRIDE UV LIGHT SENSORS ON SILICON SUBSTRATES | Nov 7, 2018 | Abandoned |