Search

Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6819100 [patent_doc_number] => 20030070058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Method and device for a context-based memory management system' [patent_app_type] => new [patent_app_number] => 09/973279 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3083 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20030070058.pdf [firstpage_image] =>[orig_patent_app_number] => 09973279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973279
Method and device for a context-based memory management system Oct 8, 2001 Issued
Array ( [id] => 1097383 [patent_doc_number] => 06826675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-30 [patent_title] => 'Stack utilization management system and method for a single-stack arrangement' [patent_app_type] => B1 [patent_app_number] => 09/973156 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6658 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826675.pdf [firstpage_image] =>[orig_patent_app_number] => 09973156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973156
Stack utilization management system and method for a single-stack arrangement Oct 8, 2001 Issued
Array ( [id] => 1129663 [patent_doc_number] => 06795910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Stack utilization management system and method for a two-stack arrangement' [patent_app_type] => B1 [patent_app_number] => 09/973665 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6889 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795910.pdf [firstpage_image] =>[orig_patent_app_number] => 09973665 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973665
Stack utilization management system and method for a two-stack arrangement Oct 8, 2001 Issued
Array ( [id] => 6819088 [patent_doc_number] => 20030070046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Method and apparatus for cache space allocation' [patent_app_type] => new [patent_app_number] => 09/975763 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2073 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20030070046.pdf [firstpage_image] =>[orig_patent_app_number] => 09975763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975763
Method and apparatus for cache space allocation Oct 8, 2001 Issued
Array ( [id] => 6819089 [patent_doc_number] => 20030070047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Method and apparatus for adaptive cache frame locking and unlocking' [patent_app_type] => new [patent_app_number] => 09/975764 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3328 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20030070047.pdf [firstpage_image] =>[orig_patent_app_number] => 09975764 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975764
Method and apparatus for adaptive cache frame locking and unlocking Oct 8, 2001 Issued
Array ( [id] => 6819087 [patent_doc_number] => 20030070045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Method and apparatus for reducing cache thrashing' [patent_app_type] => new [patent_app_number] => 09/975762 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4193 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20030070045.pdf [firstpage_image] =>[orig_patent_app_number] => 09975762 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975762
Method and apparatus for reducing cache thrashing Oct 8, 2001 Issued
Array ( [id] => 1161372 [patent_doc_number] => 06775737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Method and apparatus for allocating and using range identifiers as input values to content-addressable memories' [patent_app_type] => B1 [patent_app_number] => 09/973508 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4289 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775737.pdf [firstpage_image] =>[orig_patent_app_number] => 09973508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/973508
Method and apparatus for allocating and using range identifiers as input values to content-addressable memories Oct 8, 2001 Issued
Array ( [id] => 6757470 [patent_doc_number] => 20030005247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Memory access using system management interrupt and associated computer system' [patent_app_type] => new [patent_app_number] => 09/974245 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3018 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20030005247.pdf [firstpage_image] =>[orig_patent_app_number] => 09974245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974245
Memory access using system management interrupt and associated computer system Oct 8, 2001 Issued
Array ( [id] => 6818980 [patent_doc_number] => 20030069938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Shared memory coupling of network infrastructure devices' [patent_app_type] => new [patent_app_number] => 09/971135 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9056 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20030069938.pdf [firstpage_image] =>[orig_patent_app_number] => 09971135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971135
Shared memory coupling of network infrastructure devices Oct 3, 2001 Issued
Array ( [id] => 1037270 [patent_doc_number] => 06877145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Automatic generation of interconnect logic components' [patent_app_type] => utility [patent_app_number] => 09/919806 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11889 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877145.pdf [firstpage_image] =>[orig_patent_app_number] => 09919806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919806
Automatic generation of interconnect logic components Aug 1, 2001 Issued
Array ( [id] => 6839778 [patent_doc_number] => 20030037118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Private memory access in multi-node system' [patent_app_type] => new [patent_app_number] => 09/921841 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037118.pdf [firstpage_image] =>[orig_patent_app_number] => 09921841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921841
Private memory access in multi-node system Aug 1, 2001 Issued
Array ( [id] => 1097218 [patent_doc_number] => 06826622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Method of transferring data between memories of computers' [patent_app_type] => B2 [patent_app_number] => 09/918639 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7054 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826622.pdf [firstpage_image] =>[orig_patent_app_number] => 09918639 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/918639
Method of transferring data between memories of computers Jul 31, 2001 Issued
Array ( [id] => 1037167 [patent_doc_number] => 06877091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Actuation of projector by system stored in mobile memory' [patent_app_type] => utility [patent_app_number] => 10/019647 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4996 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877091.pdf [firstpage_image] =>[orig_patent_app_number] => 10019647 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/019647
Actuation of projector by system stored in mobile memory Jul 10, 2001 Issued
Array ( [id] => 1242676 [patent_doc_number] => RE038388 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method and apparatus for performing deferred transactions' [patent_app_type] => E1 [patent_app_number] => 09/882444 [patent_app_country] => US [patent_app_date] => 2001-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 10826 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/038/RE038388.pdf [firstpage_image] =>[orig_patent_app_number] => 09882444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882444
Method and apparatus for performing deferred transactions Jun 13, 2001 Issued
Array ( [id] => 6551909 [patent_doc_number] => 20020194290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch' [patent_app_type] => new [patent_app_number] => 09/843228 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3780 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194290.pdf [firstpage_image] =>[orig_patent_app_number] => 09843228 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843228
Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch Apr 25, 2001 Issued
Array ( [id] => 5803374 [patent_doc_number] => 20020010752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Information processing apparatus, method thereof, information processing system, and medium' [patent_app_type] => new [patent_app_number] => 09/819399 [patent_app_country] => US [patent_app_date] => 2001-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8491 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010752.pdf [firstpage_image] =>[orig_patent_app_number] => 09819399 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/819399
Information processing apparatus, method thereof, information processing system, and medium Mar 27, 2001 Abandoned
Array ( [id] => 1601981 [patent_doc_number] => 06385692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-07 [patent_title] => 'Methods and apparatus for variable length SDRAM transfers' [patent_app_type] => B2 [patent_app_number] => 09/805588 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 4138 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385692.pdf [firstpage_image] =>[orig_patent_app_number] => 09805588 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/805588
Methods and apparatus for variable length SDRAM transfers Mar 11, 2001 Issued
Array ( [id] => 7610019 [patent_doc_number] => 06842840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Controller which determines presence of memory in a node of a data network' [patent_app_type] => utility [patent_app_number] => 09/793751 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6857 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842840.pdf [firstpage_image] =>[orig_patent_app_number] => 09793751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/793751
Controller which determines presence of memory in a node of a data network Feb 26, 2001 Issued
Array ( [id] => 1206868 [patent_doc_number] => 06721850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'Method of cache replacement for streaming media' [patent_app_type] => B2 [patent_app_number] => 09/794379 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 6404 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/721/06721850.pdf [firstpage_image] =>[orig_patent_app_number] => 09794379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794379
Method of cache replacement for streaming media Feb 26, 2001 Issued
Array ( [id] => 6532060 [patent_doc_number] => 20020026567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Processor capable of enabling/disabling memory access' [patent_app_type] => new [patent_app_number] => 09/791874 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2202 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20020026567.pdf [firstpage_image] =>[orig_patent_app_number] => 09791874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/791874
Processor capable of enabling/disabling memory access Feb 25, 2001 Issued
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