Search

Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1533143 [patent_doc_number] => 06480939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Method and apparatus for filtering prefetches to provide high prefetch accuracy using less hardware' [patent_app_type] => B2 [patent_app_number] => 09/751800 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5691 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480939.pdf [firstpage_image] =>[orig_patent_app_number] => 09751800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751800
Method and apparatus for filtering prefetches to provide high prefetch accuracy using less hardware Dec 28, 2000 Issued
Array ( [id] => 6648390 [patent_doc_number] => 20020087804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture' [patent_app_type] => new [patent_app_number] => 09/752937 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087804.pdf [firstpage_image] =>[orig_patent_app_number] => 09752937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752937
Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture Dec 28, 2000 Issued
Array ( [id] => 1250242 [patent_doc_number] => 06675266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors' [patent_app_type] => B2 [patent_app_number] => 09/750094 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5899 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675266.pdf [firstpage_image] =>[orig_patent_app_number] => 09750094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750094
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors Dec 28, 2000 Issued
Array ( [id] => 6648206 [patent_doc_number] => 20020087783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Low cost, high performance tape drive' [patent_app_type] => new [patent_app_number] => 09/751755 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6976 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087783.pdf [firstpage_image] =>[orig_patent_app_number] => 09751755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751755
Low cost, high performance tape drive Dec 28, 2000 Abandoned
Array ( [id] => 6648595 [patent_doc_number] => 20020087824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'System and method for employing a process identifier to minimize aliasing in a linear-addressed cache' [patent_app_type] => new [patent_app_number] => 09/751258 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3771 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087824.pdf [firstpage_image] =>[orig_patent_app_number] => 09751258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751258
System and method for employing a process identifier to minimize aliasing in a linear-addressed cache Dec 28, 2000 Abandoned
Array ( [id] => 1314393 [patent_doc_number] => 06622215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Mechanism for handling conflicts in a multi-node computer architecture' [patent_app_type] => B2 [patent_app_number] => 09/753263 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4561 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622215.pdf [firstpage_image] =>[orig_patent_app_number] => 09753263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/753263
Mechanism for handling conflicts in a multi-node computer architecture Dec 28, 2000 Issued
Array ( [id] => 6648177 [patent_doc_number] => 20020087779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'High-speed way select scheme for a low power cache' [patent_app_type] => new [patent_app_number] => 09/752873 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2321 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087779.pdf [firstpage_image] =>[orig_patent_app_number] => 09752873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752873
High-speed way select scheme for a low power cache Dec 28, 2000 Abandoned
Array ( [id] => 1573757 [patent_doc_number] => 06499085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-24 [patent_title] => 'Method and system for servicing cache line in response to partial cache line request' [patent_app_type] => B2 [patent_app_number] => 09/752846 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5602 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499085.pdf [firstpage_image] =>[orig_patent_app_number] => 09752846 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752846
Method and system for servicing cache line in response to partial cache line request Dec 28, 2000 Issued
Array ( [id] => 6648184 [patent_doc_number] => 20020087780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Floating virtualization layers' [patent_app_type] => new [patent_app_number] => 09/752071 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5668 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087780.pdf [firstpage_image] =>[orig_patent_app_number] => 09752071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752071
Floating virtualization layers Dec 28, 2000 Issued
Array ( [id] => 1418852 [patent_doc_number] => 06546472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Fast suspend to disk' [patent_app_type] => B2 [patent_app_number] => 09/751165 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 10011 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546472.pdf [firstpage_image] =>[orig_patent_app_number] => 09751165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751165
Fast suspend to disk Dec 28, 2000 Issued
Array ( [id] => 6648340 [patent_doc_number] => 20020087799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Circuit and method for hardware-assisted software flushing of data and instruction caches' [patent_app_type] => new [patent_app_number] => 09/751371 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087799.pdf [firstpage_image] =>[orig_patent_app_number] => 09751371 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751371
Circuit and method for hardware-assisted software flushing of data and instruction caches Dec 28, 2000 Issued
Array ( [id] => 6648353 [patent_doc_number] => 20020087800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'System and method for prefetching data into a cache based on miss distance' [patent_app_type] => new [patent_app_number] => 09/749936 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5670 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087800.pdf [firstpage_image] =>[orig_patent_app_number] => 09749936 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749936
System and method for prefetching data into a cache based on miss distance Dec 28, 2000 Issued
Array ( [id] => 1460022 [patent_doc_number] => 06463510 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Apparatus for identifying memory requests originating on remote I/O devices as noncacheable' [patent_app_type] => B1 [patent_app_number] => 09/751505 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463510.pdf [firstpage_image] =>[orig_patent_app_number] => 09751505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751505
Apparatus for identifying memory requests originating on remote I/O devices as noncacheable Dec 28, 2000 Issued
Array ( [id] => 6648473 [patent_doc_number] => 20020087810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model' [patent_app_type] => new [patent_app_number] => 09/750133 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5497 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087810.pdf [firstpage_image] =>[orig_patent_app_number] => 09750133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750133
System and method for high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model Dec 28, 2000 Issued
Array ( [id] => 1418691 [patent_doc_number] => 06546458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method and apparatus for arbitrarily large capacity removable media' [patent_app_type] => B2 [patent_app_number] => 09/751572 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9702 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546458.pdf [firstpage_image] =>[orig_patent_app_number] => 09751572 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751572
Method and apparatus for arbitrarily large capacity removable media Dec 28, 2000 Issued
Array ( [id] => 1279550 [patent_doc_number] => 06654862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'High performance disk mirroring' [patent_app_type] => B2 [patent_app_number] => 09/752356 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654862.pdf [firstpage_image] =>[orig_patent_app_number] => 09752356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752356
High performance disk mirroring Dec 28, 2000 Issued
Array ( [id] => 6648286 [patent_doc_number] => 20020087793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'System and method for instruction cache re-ordering' [patent_app_type] => new [patent_app_number] => 09/752414 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3597 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20020087793.pdf [firstpage_image] =>[orig_patent_app_number] => 09752414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752414
System and method for instruction cache re-ordering Dec 28, 2000 Issued
Array ( [id] => 765154 [patent_doc_number] => 07017008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device' [patent_app_type] => utility [patent_app_number] => 09/751602 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1707 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/017/07017008.pdf [firstpage_image] =>[orig_patent_app_number] => 09751602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751602
Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device Dec 28, 2000 Issued
Array ( [id] => 7621145 [patent_doc_number] => 06978356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'System to support dynamically flexible data definitions and storage requirements' [patent_app_type] => utility [patent_app_number] => 09/751635 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4570 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/978/06978356.pdf [firstpage_image] =>[orig_patent_app_number] => 09751635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751635
System to support dynamically flexible data definitions and storage requirements Dec 28, 2000 Issued
Array ( [id] => 1493454 [patent_doc_number] => 06418078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-09 [patent_title] => 'Synchronous DRAM device having a control data buffer' [patent_app_type] => B2 [patent_app_number] => 09/745892 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6474 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 426 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418078.pdf [firstpage_image] =>[orig_patent_app_number] => 09745892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745892
Synchronous DRAM device having a control data buffer Dec 20, 2000 Issued
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