Search

Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5926031 [patent_doc_number] => 20020116448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Cofetching in a command cache' [patent_app_type] => new [patent_app_number] => 09/740399 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116448.pdf [firstpage_image] =>[orig_patent_app_number] => 09740399 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740399
Cofetching in a command cache Dec 17, 2000 Issued
Array ( [id] => 1580339 [patent_doc_number] => 06470426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method and apparatus for loading a cache with data with a subsequent purge of stale cache information' [patent_app_type] => B2 [patent_app_number] => 09/738063 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3510 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470426.pdf [firstpage_image] =>[orig_patent_app_number] => 09738063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738063
Method and apparatus for loading a cache with data with a subsequent purge of stale cache information Dec 14, 2000 Issued
Array ( [id] => 1540585 [patent_doc_number] => 06490668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-03 [patent_title] => 'System and method for dynamically moving checksums to different memory locations' [patent_app_type] => B2 [patent_app_number] => 09/738697 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11652 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490668.pdf [firstpage_image] =>[orig_patent_app_number] => 09738697 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738697
System and method for dynamically moving checksums to different memory locations Dec 14, 2000 Issued
Array ( [id] => 6133997 [patent_doc_number] => 20020078307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Memory-to-memory copy and compare/exchange instructions to support non-blocking synchronization schemes' [patent_app_type] => new [patent_app_number] => 09/736433 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4690 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20020078307.pdf [firstpage_image] =>[orig_patent_app_number] => 09736433 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736433
Memory-to-memory compare/exchange instructions to support non-blocking synchronization schemes Dec 14, 2000 Issued
Array ( [id] => 1428985 [patent_doc_number] => 06513100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'System and method for fast referencing a reference counted item' [patent_app_type] => B1 [patent_app_number] => 09/738568 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9051 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513100.pdf [firstpage_image] =>[orig_patent_app_number] => 09738568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738568
System and method for fast referencing a reference counted item Dec 14, 2000 Issued
Array ( [id] => 1533140 [patent_doc_number] => 06480938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Efficient I-cache structure to support instructions crossing line boundaries' [patent_app_type] => B2 [patent_app_number] => 09/738690 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 10684 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480938.pdf [firstpage_image] =>[orig_patent_app_number] => 09738690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/738690
Efficient I-cache structure to support instructions crossing line boundaries Dec 14, 2000 Issued
Array ( [id] => 4298439 [patent_doc_number] => 06282604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Memory controller and method for meory devices with mutliple banks of memory cells' [patent_app_type] => 1 [patent_app_number] => 9/665731 [patent_app_country] => US [patent_app_date] => 2000-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6654 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282604.pdf [firstpage_image] =>[orig_patent_app_number] => 665731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/665731
Memory controller and method for meory devices with mutliple banks of memory cells Sep 19, 2000 Issued
Array ( [id] => 1429251 [patent_doc_number] => 06529997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Apparatus and method for writing and reading data to and from a virtual volume of redundant storage devices' [patent_app_type] => B1 [patent_app_number] => 09/638205 [patent_app_country] => US [patent_app_date] => 2000-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6533 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529997.pdf [firstpage_image] =>[orig_patent_app_number] => 09638205 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638205
Apparatus and method for writing and reading data to and from a virtual volume of redundant storage devices Aug 10, 2000 Issued
Array ( [id] => 1538461 [patent_doc_number] => 06337821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Dynamic random access memory having continuous data line equalization except at address translation during data reading' [patent_app_type] => B1 [patent_app_number] => 09/636504 [patent_app_country] => US [patent_app_date] => 2000-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4642 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337821.pdf [firstpage_image] =>[orig_patent_app_number] => 09636504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/636504
Dynamic random access memory having continuous data line equalization except at address translation during data reading Aug 9, 2000 Issued
Array ( [id] => 1572307 [patent_doc_number] => 06378032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Bank conflict avoidance in multi-bank DRAMS with shared sense amplifiers' [patent_app_type] => B1 [patent_app_number] => 09/616279 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4974 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378032.pdf [firstpage_image] =>[orig_patent_app_number] => 09616279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/616279
Bank conflict avoidance in multi-bank DRAMS with shared sense amplifiers Jul 13, 2000 Issued
Array ( [id] => 947587 [patent_doc_number] => 06965922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-15 [patent_title] => 'Computer system and method with internal use of networking switching' [patent_app_type] => utility [patent_app_number] => 09/551790 [patent_app_country] => US [patent_app_date] => 2000-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5528 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965922.pdf [firstpage_image] =>[orig_patent_app_number] => 09551790 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/551790
Computer system and method with internal use of networking switching Apr 17, 2000 Issued
Array ( [id] => 4298705 [patent_doc_number] => 06282623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Method for digital signal processing, DSP, mobile communication and audi o-device' [patent_app_type] => 1 [patent_app_number] => 9/497986 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5324 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282623.pdf [firstpage_image] =>[orig_patent_app_number] => 497986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497986
Method for digital signal processing, DSP, mobile communication and audi o-device Feb 3, 2000 Issued
Array ( [id] => 4374630 [patent_doc_number] => 06170038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Trace based instruction caching' [patent_app_type] => 1 [patent_app_number] => 9/447078 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7927 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170038.pdf [firstpage_image] =>[orig_patent_app_number] => 447078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447078
Trace based instruction caching Nov 21, 1999 Issued
Array ( [id] => 1524857 [patent_doc_number] => 06415353 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same' [patent_app_type] => B1 [patent_app_number] => 09/405607 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 25628 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415353.pdf [firstpage_image] =>[orig_patent_app_number] => 09405607 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405607
Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same Sep 23, 1999 Issued
Array ( [id] => 1462442 [patent_doc_number] => 06427197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations' [patent_app_type] => B1 [patent_app_number] => 09/394891 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 34 [patent_no_of_words] => 21836 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427197.pdf [firstpage_image] =>[orig_patent_app_number] => 09394891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394891
Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations Sep 12, 1999 Issued
09/394222 SYSTEM AND METHOD FOR RE-ORDERING MEMORY REFERENCES IN A MEMORY CONTROL SYSTEM TO SPEED ACCESS TO MEMORY CELLS Sep 12, 1999 Abandoned
Array ( [id] => 1271934 [patent_doc_number] => 06662292 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Memory access system' [patent_app_type] => B1 [patent_app_number] => 09/395295 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4154 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662292.pdf [firstpage_image] =>[orig_patent_app_number] => 09395295 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395295
Memory access system Sep 12, 1999 Issued
Array ( [id] => 1540551 [patent_doc_number] => 06490655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Data processing apparatus and method for cache line replacement responsive to the operational state of memory' [patent_app_type] => B1 [patent_app_number] => 09/394424 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6595 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490655.pdf [firstpage_image] =>[orig_patent_app_number] => 09394424 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394424
Data processing apparatus and method for cache line replacement responsive to the operational state of memory Sep 12, 1999 Issued
Array ( [id] => 1481694 [patent_doc_number] => 06345335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Data processing memory system' [patent_app_type] => B1 [patent_app_number] => 09/394425 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2927 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345335.pdf [firstpage_image] =>[orig_patent_app_number] => 09394425 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394425
Data processing memory system Sep 12, 1999 Issued
Array ( [id] => 1567464 [patent_doc_number] => 06363466 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Interface and process for handling out-of-order data transactions and synchronizing events in a split-bus system' [patent_app_type] => B1 [patent_app_number] => 09/394395 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4462 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363466.pdf [firstpage_image] =>[orig_patent_app_number] => 09394395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394395
Interface and process for handling out-of-order data transactions and synchronizing events in a split-bus system Sep 12, 1999 Issued
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