Search

Telly D. Green

Examiner (ID: 3638, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2898, 2809
Total Applications
1746
Issued Applications
1383
Pending Applications
135
Abandoned Applications
254

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18927172 [patent_doc_number] => 20240030176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/112323 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18112323 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/112323
Method of fabricating semiconductor package Feb 20, 2023 Issued
Array ( [id] => 19107029 [patent_doc_number] => 11960127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/167077 [patent_app_country] => US [patent_app_date] => 2023-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 11330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18167077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/167077
Semiconductor package and manufacturing method thereof Feb 9, 2023 Issued
Array ( [id] => 18582691 [patent_doc_number] => 20230264946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => Ultra-High Frequency MEMS Resonators with First and Second Order Temperature-Induced Frequency Drift Compensation [patent_app_type] => utility [patent_app_number] => 18/166838 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166838 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166838
Ultra-High Frequency MEMS Resonators with First and Second Order Temperature-Induced Frequency Drift Compensation Feb 8, 2023 Pending
Array ( [id] => 18382095 [patent_doc_number] => 20230157186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => NON-STOICHIOMETRIC RESISTIVE SWITCHING MEMORY DEVICE AND FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 18/097748 [patent_app_country] => US [patent_app_date] => 2023-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18097748 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/097748
Non-stoichiometric resistive switching memory device and fabrication methods Jan 16, 2023 Issued
Array ( [id] => 20705963 [patent_doc_number] => 12628695 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Packaging structure and packaging method [patent_app_type] => utility [patent_app_number] => 18/096088 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 4622 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18096088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/096088
Packaging structure and packaging method Jan 11, 2023 Issued
Array ( [id] => 19887030 [patent_doc_number] => 12272764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Advanced electronic device structures using semiconductor structures and superlattices [patent_app_type] => utility [patent_app_number] => 18/152452 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 61 [patent_no_of_words] => 15361 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152452 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152452
Advanced electronic device structures using semiconductor structures and superlattices Jan 9, 2023 Issued
Array ( [id] => 19285815 [patent_doc_number] => 20240222292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => Method for Sigulating Semiconductor Devices and Package Device Including the Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/152626 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152626 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/152626
Method for Sigulating Semiconductor Devices and Package Device Including the Semiconductor Devices Jan 9, 2023 Pending
Array ( [id] => 19269532 [patent_doc_number] => 20240213236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => INTEGRATED CIRCUIT PACKAGE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/151629 [patent_app_country] => US [patent_app_date] => 2023-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151629
INTEGRATED CIRCUIT PACKAGE AND METHOD Jan 8, 2023 Pending
Array ( [id] => 19071106 [patent_doc_number] => 20240105532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/149077 [patent_app_country] => US [patent_app_date] => 2022-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149077
CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE Dec 30, 2022 Pending
Array ( [id] => 19286036 [patent_doc_number] => 20240222514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => ETCH STOP FOR OXIDE SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/090056 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090056
ETCH STOP FOR OXIDE SEMICONDUCTOR DEVICES Dec 27, 2022 Pending
Array ( [id] => 19269506 [patent_doc_number] => 20240213210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SYSTEM AND METHOD FOR USING ACOUSTIC WAVES TO COUNTERACT DEFORMATIONS DURING BONDING [patent_app_type] => utility [patent_app_number] => 18/146265 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146265
SYSTEM AND METHOD FOR USING ACOUSTIC WAVES TO COUNTERACT DEFORMATIONS DURING BONDING Dec 22, 2022 Pending
Array ( [id] => 19269696 [patent_doc_number] => 20240213401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => TEXTURED LUMIPHORE LAYER TO IMPROVE LIGHT EXTRACTION FOR LIGHT-EMITTING DIODE CHIPS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/085672 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085672 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/085672
TEXTURED LUMIPHORE LAYER TO IMPROVE LIGHT EXTRACTION FOR LIGHT-EMITTING DIODE CHIPS AND RELATED METHODS Dec 20, 2022 Pending
Array ( [id] => 19110224 [patent_doc_number] => 11963357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Nonvolatile memory device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 18/065799 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 15753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18065799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/065799
Nonvolatile memory device and method for fabricating the same Dec 13, 2022 Issued
Array ( [id] => 19244554 [patent_doc_number] => 12015009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Stacked semiconductor die architecture with multiple layers of disaggregation [patent_app_type] => utility [patent_app_number] => 18/080610 [patent_app_country] => US [patent_app_date] => 2022-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8281 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18080610 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/080610
Stacked semiconductor die architecture with multiple layers of disaggregation Dec 12, 2022 Issued
Array ( [id] => 19221565 [patent_doc_number] => 20240186269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => BONDED STRUCTURE WITH SECURITY DIE [patent_app_type] => utility [patent_app_number] => 18/061383 [patent_app_country] => US [patent_app_date] => 2022-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061383 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061383
BONDED STRUCTURE WITH SECURITY DIE Dec 1, 2022 Pending
Array ( [id] => 18379727 [patent_doc_number] => 20230154816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => THERMAL BYPASS FOR STACKED DIES [patent_app_type] => utility [patent_app_number] => 18/055798 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18055798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/055798
THERMAL BYPASS FOR STACKED DIES Nov 14, 2022 Pending
Array ( [id] => 19488913 [patent_doc_number] => 12108658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Light-emitting device [patent_app_type] => utility [patent_app_number] => 17/987188 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 15095 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17987188 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/987188
Light-emitting device Nov 14, 2022 Issued
Array ( [id] => 18244828 [patent_doc_number] => 20230077139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => Semiconductor Package Having an Electrically Insulating Core with Exposed Glass Fibres [patent_app_type] => utility [patent_app_number] => 17/986306 [patent_app_country] => US [patent_app_date] => 2022-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17986306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/986306
Semiconductor package having an electrically insulating core with exposed glass fibres Nov 13, 2022 Issued
Array ( [id] => 19176152 [patent_doc_number] => 20240162126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/054919 [patent_app_country] => US [patent_app_date] => 2022-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054919
Semiconductor package and manufacturing method thereof Nov 13, 2022 Issued
Array ( [id] => 18222164 [patent_doc_number] => 20230061158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => Semiconductor Device with Multi-Layer Dielectric and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 18/047412 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18047412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/047412
Semiconductor device with multi-layer dielectric Oct 17, 2022 Issued
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