Search

Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3954739 [patent_doc_number] => 05900007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Data storage disk array having a constraint function for spatially dispersing disk files in the disk array' [patent_app_type] => 1 [patent_app_number] => 8/698155 [patent_app_country] => US [patent_app_date] => 1996-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7067 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900007.pdf [firstpage_image] =>[orig_patent_app_number] => 698155 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/698155
Data storage disk array having a constraint function for spatially dispersing disk files in the disk array Aug 6, 1996 Issued
Array ( [id] => 3907923 [patent_doc_number] => 05778408 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Cache addressing mechanism that adapts multi-dimensional addressing topology' [patent_app_type] => 1 [patent_app_number] => 8/691451 [patent_app_country] => US [patent_app_date] => 1996-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1987 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778408.pdf [firstpage_image] =>[orig_patent_app_number] => 691451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691451
Cache addressing mechanism that adapts multi-dimensional addressing topology Aug 1, 1996 Issued
Array ( [id] => 3797971 [patent_doc_number] => 05809519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Systems and methods to convert signals multiplexed on a single wire to three wire' [patent_app_type] => 1 [patent_app_number] => 8/688420 [patent_app_country] => US [patent_app_date] => 1996-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 48 [patent_no_of_words] => 22171 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809519.pdf [firstpage_image] =>[orig_patent_app_number] => 688420 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/688420
Systems and methods to convert signals multiplexed on a single wire to three wire Jul 29, 1996 Issued
Array ( [id] => 4064784 [patent_doc_number] => 05870574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'System and method for fetching multiple groups of instructions from an instruction cache in a RISC processor system for execution during separate cycles' [patent_app_type] => 1 [patent_app_number] => 8/686363 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1882 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870574.pdf [firstpage_image] =>[orig_patent_app_number] => 686363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/686363
System and method for fetching multiple groups of instructions from an instruction cache in a RISC processor system for execution during separate cycles Jul 23, 1996 Issued
Array ( [id] => 3888807 [patent_doc_number] => 05893930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer' [patent_app_type] => 1 [patent_app_number] => 8/678940 [patent_app_country] => US [patent_app_date] => 1996-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893930.pdf [firstpage_image] =>[orig_patent_app_number] => 678940 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/678940
Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer Jul 11, 1996 Issued
Array ( [id] => 3898072 [patent_doc_number] => 05765193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'System for controlling a write operation involving data held in a write cache' [patent_app_type] => 1 [patent_app_number] => 8/680583 [patent_app_country] => US [patent_app_date] => 1996-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4693 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765193.pdf [firstpage_image] =>[orig_patent_app_number] => 680583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/680583
System for controlling a write operation involving data held in a write cache Jul 8, 1996 Issued
Array ( [id] => 3974352 [patent_doc_number] => 05937171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method and apparatus for performing deferred transactions' [patent_app_type] => 1 [patent_app_number] => 8/669101 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 10746 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937171.pdf [firstpage_image] =>[orig_patent_app_number] => 669101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/669101
Method and apparatus for performing deferred transactions Jun 25, 1996 Issued
Array ( [id] => 3973315 [patent_doc_number] => 05978883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Block interleaving and deinterleaving method and device therefor' [patent_app_type] => 1 [patent_app_number] => 8/495548 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4601 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978883.pdf [firstpage_image] =>[orig_patent_app_number] => 495548 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/495548
Block interleaving and deinterleaving method and device therefor Jun 25, 1996 Issued
Array ( [id] => 3898412 [patent_doc_number] => 05765216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Data processor with an efficient bit move capability and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/665927 [patent_app_country] => US [patent_app_date] => 1996-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4634 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765216.pdf [firstpage_image] =>[orig_patent_app_number] => 665927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665927
Data processor with an efficient bit move capability and method therefor Jun 16, 1996 Issued
Array ( [id] => 4073015 [patent_doc_number] => 05864872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Single wire communication system' [patent_app_type] => 1 [patent_app_number] => 8/654464 [patent_app_country] => US [patent_app_date] => 1996-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 48 [patent_no_of_words] => 22134 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864872.pdf [firstpage_image] =>[orig_patent_app_number] => 654464 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/654464
Single wire communication system May 27, 1996 Issued
Array ( [id] => 3701746 [patent_doc_number] => 05604879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Single array address translator with segment and page invalidate ability and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/653677 [patent_app_country] => US [patent_app_date] => 1996-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 12382 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604879.pdf [firstpage_image] =>[orig_patent_app_number] => 653677 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653677
Single array address translator with segment and page invalidate ability and method of operation May 22, 1996 Issued
Array ( [id] => 3797952 [patent_doc_number] => 05809518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Command/data transfer protocol for one-wire-bus architecture' [patent_app_type] => 1 [patent_app_number] => 8/650664 [patent_app_country] => US [patent_app_date] => 1996-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 49 [patent_no_of_words] => 22169 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809518.pdf [firstpage_image] =>[orig_patent_app_number] => 650664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/650664
Command/data transfer protocol for one-wire-bus architecture May 19, 1996 Issued
Array ( [id] => 3843541 [patent_doc_number] => 05784708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Translation mechanism for input/output addresses' [patent_app_type] => 1 [patent_app_number] => 8/647074 [patent_app_country] => US [patent_app_date] => 1996-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3022 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784708.pdf [firstpage_image] =>[orig_patent_app_number] => 647074 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/647074
Translation mechanism for input/output addresses May 7, 1996 Issued
Array ( [id] => 3893658 [patent_doc_number] => 05729709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Memory controller with burst addressing circuit' [patent_app_type] => 1 [patent_app_number] => 8/618611 [patent_app_country] => US [patent_app_date] => 1996-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5431 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729709.pdf [firstpage_image] =>[orig_patent_app_number] => 618611 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/618611
Memory controller with burst addressing circuit Mar 20, 1996 Issued
Array ( [id] => 3902563 [patent_doc_number] => 05724538 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Computer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computer' [patent_app_type] => 1 [patent_app_number] => 8/607622 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4004 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724538.pdf [firstpage_image] =>[orig_patent_app_number] => 607622 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/607622
Computer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computer Feb 26, 1996 Issued
Array ( [id] => 4029285 [patent_doc_number] => 05883324 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Signal generating apparatus and signal generating method' [patent_app_type] => 1 [patent_app_number] => 8/572714 [patent_app_country] => US [patent_app_date] => 1995-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 20109 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883324.pdf [firstpage_image] =>[orig_patent_app_number] => 572714 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/572714
Signal generating apparatus and signal generating method Dec 13, 1995 Issued
Array ( [id] => 4029541 [patent_doc_number] => RE036229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Simulcast standard multichip memory addressing system' [patent_app_type] => 2 [patent_app_number] => 8/510729 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2838 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036229.pdf [firstpage_image] =>[orig_patent_app_number] => 510729 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/510729
Simulcast standard multichip memory addressing system Nov 19, 1995 Issued
Array ( [id] => 3603550 [patent_doc_number] => 05586284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Triple register RISC digital signal processor' [patent_app_type] => 1 [patent_app_number] => 8/547050 [patent_app_country] => US [patent_app_date] => 1995-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6379 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586284.pdf [firstpage_image] =>[orig_patent_app_number] => 547050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/547050
Triple register RISC digital signal processor Oct 22, 1995 Issued
Array ( [id] => 3907952 [patent_doc_number] => 05778412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Method and apparatus for interfacing a data bus to a plurality of memory devices' [patent_app_type] => 1 [patent_app_number] => 8/536378 [patent_app_country] => US [patent_app_date] => 1995-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5877 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778412.pdf [firstpage_image] =>[orig_patent_app_number] => 536378 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/536378
Method and apparatus for interfacing a data bus to a plurality of memory devices Sep 28, 1995 Issued
Array ( [id] => 3867817 [patent_doc_number] => 05706243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Semiconductor memory and method of using the same, column decoder, and image processor' [patent_app_type] => 1 [patent_app_number] => 8/534098 [patent_app_country] => US [patent_app_date] => 1995-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 11533 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706243.pdf [firstpage_image] =>[orig_patent_app_number] => 534098 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/534098
Semiconductor memory and method of using the same, column decoder, and image processor Sep 25, 1995 Issued
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