Search

Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3999027 [patent_doc_number] => 05920096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Electrostatic discharge protection systems and methods for electronic tokens' [patent_app_type] => 1 [patent_app_number] => 8/348513 [patent_app_country] => US [patent_app_date] => 1994-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 48 [patent_no_of_words] => 22134 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920096.pdf [firstpage_image] =>[orig_patent_app_number] => 348513 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/348513
Electrostatic discharge protection systems and methods for electronic tokens Nov 30, 1994 Issued
08/347913 SYSTEMS AND METHODS TO CORRECT SIGNALS MULTIPLEXED ON A SINGLE WIRE TO THREE WIRE Nov 30, 1994 Abandoned
Array ( [id] => 3616550 [patent_doc_number] => 05579501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-26 [patent_title] => 'Method for transforming a hash bucket number to a control interval to identify the physical location of information in a mass memory' [patent_app_type] => 1 [patent_app_number] => 8/347005 [patent_app_country] => US [patent_app_date] => 1994-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2740 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/579/05579501.pdf [firstpage_image] =>[orig_patent_app_number] => 347005 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/347005
Method for transforming a hash bucket number to a control interval to identify the physical location of information in a mass memory Nov 29, 1994 Issued
Array ( [id] => 3747336 [patent_doc_number] => 05699300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Divided wordline memory arrangement having overlapping activation of wordlines during continuous access cycle' [patent_app_type] => 1 [patent_app_number] => 8/341947 [patent_app_country] => US [patent_app_date] => 1994-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3098 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699300.pdf [firstpage_image] =>[orig_patent_app_number] => 341947 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/341947
Divided wordline memory arrangement having overlapping activation of wordlines during continuous access cycle Nov 15, 1994 Issued
Array ( [id] => 3603521 [patent_doc_number] => 05586282 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Memory system employing pipeline process for accessing memory banks' [patent_app_type] => 1 [patent_app_number] => 8/340312 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 8081 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586282.pdf [firstpage_image] =>[orig_patent_app_number] => 340312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/340312
Memory system employing pipeline process for accessing memory banks Nov 13, 1994 Issued
Array ( [id] => 3621209 [patent_doc_number] => 05590299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Multiprocessor system bus protocol for optimized accessing of interleaved storage modules' [patent_app_type] => 1 [patent_app_number] => 8/331290 [patent_app_country] => US [patent_app_date] => 1994-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 11082 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590299.pdf [firstpage_image] =>[orig_patent_app_number] => 331290 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/331290
Multiprocessor system bus protocol for optimized accessing of interleaved storage modules Oct 27, 1994 Issued
Array ( [id] => 3561228 [patent_doc_number] => 05546555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Optimized translation lookaside buffer slice having stored mask bits' [patent_app_type] => 1 [patent_app_number] => 8/330756 [patent_app_country] => US [patent_app_date] => 1994-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 8330 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546555.pdf [firstpage_image] =>[orig_patent_app_number] => 330756 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/330756
Optimized translation lookaside buffer slice having stored mask bits Oct 27, 1994 Issued
Array ( [id] => 3532039 [patent_doc_number] => 05530820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Virtual machine and method for controlling the same' [patent_app_type] => 1 [patent_app_number] => 8/329649 [patent_app_country] => US [patent_app_date] => 1994-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 10148 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530820.pdf [firstpage_image] =>[orig_patent_app_number] => 329649 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/329649
Virtual machine and method for controlling the same Oct 24, 1994 Issued
08/324992 BRANCH PROCESSING UNIT Oct 17, 1994 Abandoned
08/324129 ADDRESS QUEUE Oct 13, 1994 Abandoned
08/324128 MEMORY TRANSLATION Oct 13, 1994 Abandoned
Array ( [id] => 3747597 [patent_doc_number] => 05699317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Enhanced DRAM with all reads from on-chip cache and all writers to memory array' [patent_app_type] => 1 [patent_app_number] => 8/319289 [patent_app_country] => US [patent_app_date] => 1994-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 14661 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699317.pdf [firstpage_image] =>[orig_patent_app_number] => 319289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/319289
Enhanced DRAM with all reads from on-chip cache and all writers to memory array Oct 5, 1994 Issued
08/310004 SEMICONDUCTOR MEMORY DEVICE WITH AN INTERNAL VOLTAGE GENERATING CIRCUIT Sep 19, 1994 Abandoned
Array ( [id] => 3504751 [patent_doc_number] => 05508960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Read/write memory with selective row write capability' [patent_app_type] => 1 [patent_app_number] => 8/303552 [patent_app_country] => US [patent_app_date] => 1994-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 16599 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508960.pdf [firstpage_image] =>[orig_patent_app_number] => 303552 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/303552
Read/write memory with selective row write capability Sep 8, 1994 Issued
Array ( [id] => 3633338 [patent_doc_number] => 05615343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method and apparatus for performing deferred transactions' [patent_app_type] => 1 [patent_app_number] => 8/302600 [patent_app_country] => US [patent_app_date] => 1994-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 10747 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615343.pdf [firstpage_image] =>[orig_patent_app_number] => 302600 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/302600
Method and apparatus for performing deferred transactions Sep 7, 1994 Issued
08/299850 DUPLICATE MESSAGE DETECTION METHOD AND APPARATUS Aug 31, 1994 Abandoned
Array ( [id] => 3699367 [patent_doc_number] => 05619066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'Memory for an electronic token' [patent_app_type] => 1 [patent_app_number] => 8/299040 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 117 [patent_no_of_words] => 42481 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619066.pdf [firstpage_image] =>[orig_patent_app_number] => 299040 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/299040
Memory for an electronic token Aug 30, 1994 Issued
Array ( [id] => 3592209 [patent_doc_number] => 05517015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Communication module' [patent_app_type] => 1 [patent_app_number] => 8/299031 [patent_app_country] => US [patent_app_date] => 1994-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 124 [patent_no_of_words] => 41458 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517015.pdf [firstpage_image] =>[orig_patent_app_number] => 299031 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/299031
Communication module Aug 30, 1994 Issued
Array ( [id] => 3536460 [patent_doc_number] => 05528551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Read/write memory with plural memory cell write capability at a selected row address' [patent_app_type] => 1 [patent_app_number] => 8/291383 [patent_app_country] => US [patent_app_date] => 1994-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 16745 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528551.pdf [firstpage_image] =>[orig_patent_app_number] => 291383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/291383
Read/write memory with plural memory cell write capability at a selected row address Aug 15, 1994 Issued
08/284801 METHOD AND APPARATUS FOR CALCULATING EFFECTIVE MEMORY ADDRESSES Aug 1, 1994 Abandoned
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