Telly D. Green

Array ( [id] => 3796682 [patent_doc_number] => 05819061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method and apparatus for dynamic storage reconfiguration in a partitioned environment' [patent_app_type] => 1 [patent_app_number] => 8/279588 [patent_app_country] => US [patent_app_date] => 1994-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819061.pdf [firstpage_image] =>[orig_patent_app_number] => 279588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3695565 [patent_doc_number] => 05634105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Semiconductor memory device to interface control signals for a DRAM to a SRAM' [patent_app_type] => 1 [patent_app_number] => 8/278332 [patent_app_country] => US [patent_app_date] => 1994-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 105 [patent_no_of_words] => 7185 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/634/05634105.pdf [firstpage_image] =>[orig_patent_app_number] => 278332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3424350 [patent_doc_number] => 05412793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-02 [patent_title] => 'Method for testing erase characteristics of a flash memory array' [patent_app_type] => 1 [patent_app_number] => 8/277369 [patent_app_country] => US [patent_app_date] => 1994-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 13686 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/412/05412793.pdf [firstpage_image] =>[orig_patent_app_number] => 277369 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3486662 [patent_doc_number] => 05428758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Method and system for remapping memory from one physical configuration to another physical configuration' [patent_app_type] => 1 [patent_app_number] => 8/270235 [patent_app_country] => US [patent_app_date] => 1994-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5240 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428758.pdf [firstpage_image] =>[orig_patent_app_number] => 270235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3734241 [patent_doc_number] => 05682494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Memory management system and method' [patent_app_type] => 1 [patent_app_number] => 8/268512 [patent_app_country] => US [patent_app_date] => 1994-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4177 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682494.pdf [firstpage_image] =>[orig_patent_app_number] => 268512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3893674 [patent_doc_number] => 05729710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Method and apparatus for management of mapped and unmapped regions of memory in a microkernel data processing system' [patent_app_type] => 1 [patent_app_number] => 8/263710 [patent_app_country] => US [patent_app_date] => 1994-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 36916 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/729/05729710.pdf [firstpage_image] =>[orig_patent_app_number] => 263710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3601324 [patent_doc_number] => 05517630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Electronic apparatus featuring a plurality of selectable memories' [patent_app_type] => 1 [patent_app_number] => 8/262379 [patent_app_country] => US [patent_app_date] => 1994-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3129 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517630.pdf [firstpage_image] =>[orig_patent_app_number] => 262379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3458187 [patent_doc_number] => 05420993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Extended address translation system for pointer updating in paged memory systems' [patent_app_type] => 1 [patent_app_number] => 8/260169 [patent_app_country] => US [patent_app_date] => 1994-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 17128 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420993.pdf [firstpage_image] =>[orig_patent_app_number] => 260169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3451415 [patent_doc_number] => 05398198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Single integrated circuit having both a memory array and an arithmetic and logic unit (ALU)' [patent_app_type] => 1 [patent_app_number] => 8/260494 [patent_app_country] => US [patent_app_date] => 1994-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4156 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/398/05398198.pdf [firstpage_image] =>[orig_patent_app_number] => 260494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3566870 [patent_doc_number] => 05502675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Semiconductor memory device having a multi-bit input/output configuration which is capable of correcting a bit failure' [patent_app_type] => 1 [patent_app_number] => 8/254412 [patent_app_country] => US [patent_app_date] => 1994-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 6627 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502675.pdf [firstpage_image] =>[orig_patent_app_number] => 254412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3530320 [patent_doc_number] => 05577219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Method and apparatus for preforming memory segment limit violation checks' [patent_app_type] => 1 [patent_app_number] => 8/236587 [patent_app_country] => US [patent_app_date] => 1994-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3600 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577219.pdf [firstpage_image] =>[orig_patent_app_number] => 236587 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3433094 [patent_doc_number] => 05422857 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Semiconductor memory unit having overlapping addresses' [patent_app_type] => 1 [patent_app_number] => 8/235263 [patent_app_country] => US [patent_app_date] => 1994-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9735 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422857.pdf [firstpage_image] =>[orig_patent_app_number] => 235263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3537219 [patent_doc_number] => 05504876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Memory apparatus having programmable memory time slots' [patent_app_type] => 1 [patent_app_number] => 8/234710 [patent_app_country] => US [patent_app_date] => 1994-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3571 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504876.pdf [firstpage_image] =>[orig_patent_app_number] => 234710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4255184 [patent_doc_number] => 06119214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method for allocation of address space in a virtual memory system' [patent_app_type] => 1 [patent_app_number] => 8/231657 [patent_app_country] => US [patent_app_date] => 1994-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6120 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119214.pdf [firstpage_image] =>[orig_patent_app_number] => 231657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3497464 [patent_doc_number] => 05426752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Method for allocating real pages to virtual pages having different page sizes therefrom' [patent_app_type] => 1 [patent_app_number] => 8/232400 [patent_app_country] => US [patent_app_date] => 1994-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 23453 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426752.pdf [firstpage_image] =>[orig_patent_app_number] => 232400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3497483 [patent_doc_number] => 05426753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Memory decoding system for portable data terminal' [patent_app_type] => 1 [patent_app_number] => 8/232577 [patent_app_country] => US [patent_app_date] => 1994-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2792 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426753.pdf [firstpage_image] =>[orig_patent_app_number] => 232577 [rel_patent_id] =>[rel_patent_doc_number] =>)