| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3532107
[patent_doc_number] => 05530825
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-25
[patent_title] => 'Data processor with branch target address cache and method of operation'
[patent_app_type] => 1
[patent_app_number] => 8/228469
[patent_app_country] => US
[patent_app_date] => 1994-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 8781
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/530/05530825.pdf
[firstpage_image] =>[orig_patent_app_number] => 228469
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/228469 | Data processor with branch target address cache and method of operation | Apr 14, 1994 | Issued |
Array
(
[id] => 3456619
[patent_doc_number] => 05388231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-07
[patent_title] => 'Enhanced VMEbus protocol utilizing pseudosynchronous handshaking and block mode data transfer'
[patent_app_type] => 1
[patent_app_number] => 8/226398
[patent_app_country] => US
[patent_app_date] => 1994-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 20
[patent_no_of_words] => 8358
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 405
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/388/05388231.pdf
[firstpage_image] =>[orig_patent_app_number] => 226398
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/226398 | Enhanced VMEbus protocol utilizing pseudosynchronous handshaking and block mode data transfer | Apr 11, 1994 | Issued |
Array
(
[id] => 3532066
[patent_doc_number] => 05530822
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-25
[patent_title] => 'Address translator and method of operation'
[patent_app_type] => 1
[patent_app_number] => 8/223067
[patent_app_country] => US
[patent_app_date] => 1994-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 12033
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/530/05530822.pdf
[firstpage_image] =>[orig_patent_app_number] => 223067
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/223067 | Address translator and method of operation | Apr 3, 1994 | Issued |
Array
(
[id] => 3626183
[patent_doc_number] => 05535351
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Address translator with by-pass circuit and method of operation'
[patent_app_type] => 1
[patent_app_number] => 8/222783
[patent_app_country] => US
[patent_app_date] => 1994-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 11986
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/535/05535351.pdf
[firstpage_image] =>[orig_patent_app_number] => 222783
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/222783 | Address translator with by-pass circuit and method of operation | Apr 3, 1994 | Issued |
Array
(
[id] => 3532096
[patent_doc_number] => 05530824
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-25
[patent_title] => 'Address translation circuit'
[patent_app_type] => 1
[patent_app_number] => 8/222779
[patent_app_country] => US
[patent_app_date] => 1994-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 11975
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/530/05530824.pdf
[firstpage_image] =>[orig_patent_app_number] => 222779
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/222779 | Address translation circuit | Apr 3, 1994 | Issued |
| 08/223266 | ADDRESS TRANSLATOR AND METHOD OF OPERATION | Apr 3, 1994 | Abandoned |
Array
(
[id] => 3500501
[patent_doc_number] => 05475827
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-12
[patent_title] => 'Dynamic look-aside table for multiple size pages'
[patent_app_type] => 1
[patent_app_number] => 8/223366
[patent_app_country] => US
[patent_app_date] => 1994-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3546
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/475/05475827.pdf
[firstpage_image] =>[orig_patent_app_number] => 223366
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/223366 | Dynamic look-aside table for multiple size pages | Mar 31, 1994 | Issued |
| 08/219263 | METHOD FOR MANAGING DATA PROCESSING SYSTEM AND HIGH-RELIABILITY MEMORY | Mar 28, 1994 | Abandoned |
Array
(
[id] => 3497566
[patent_doc_number] => 05475635
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-12
[patent_title] => 'Memory with a combined global data line load and multiplexer'
[patent_app_type] => 1
[patent_app_number] => 8/218450
[patent_app_country] => US
[patent_app_date] => 1994-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 11784
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 517
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/475/05475635.pdf
[firstpage_image] =>[orig_patent_app_number] => 218450
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/218450 | Memory with a combined global data line load and multiplexer | Mar 27, 1994 | Issued |
| 08/217536 | TRANSLATION MECHANISM FOR INPUT/OUTPUT ADDRESSES | Mar 23, 1994 | Abandoned |
Array
(
[id] => 3626197
[patent_doc_number] => 05535352
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Access hints for input/output address translation mechanisms'
[patent_app_type] => 1
[patent_app_number] => 8/217587
[patent_app_country] => US
[patent_app_date] => 1994-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4334
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/535/05535352.pdf
[firstpage_image] =>[orig_patent_app_number] => 217587
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/217587 | Access hints for input/output address translation mechanisms | Mar 23, 1994 | Issued |
| 08/216935 | ASYNCHRONOUS INTERRUPT SAFING OF PROLOGUE PORTIONS OF COMPUTER PROGRAMS | Mar 23, 1994 | Abandoned |
Array
(
[id] => 3125939
[patent_doc_number] => 05414825
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-09
[patent_title] => 'Method of programming a semiconductor memory device within a microcomputer address space'
[patent_app_type] => 1
[patent_app_number] => 8/210770
[patent_app_country] => US
[patent_app_date] => 1994-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 4834
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/414/05414825.pdf
[firstpage_image] =>[orig_patent_app_number] => 210770
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/210770 | Method of programming a semiconductor memory device within a microcomputer address space | Mar 20, 1994 | Issued |
| 08/214285 | DATA PROCESSING SYSTEM WITH DYNAMIC ADDRESS TRANSLATION FUNCTION | Mar 16, 1994 | Abandoned |
| 08/212121 | MEMORY ACCESS CONTROL DEVICE WITH PREFETCH AND READ OUT BLOCK LENGTH CONTROL FUNCTIONS | Mar 13, 1994 | Abandoned |
| 08/209499 | GENERAL-PURPOSE, CUSTOMIZABLE MEMORY CONTROLLER | Mar 13, 1994 | Abandoned |
Array
(
[id] => 3432393
[patent_doc_number] => 05479630
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same'
[patent_app_type] => 1
[patent_app_number] => 8/212377
[patent_app_country] => US
[patent_app_date] => 1994-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 5512
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479630.pdf
[firstpage_image] =>[orig_patent_app_number] => 212377
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/212377 | Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same | Mar 10, 1994 | Issued |
Array
(
[id] => 3117820
[patent_doc_number] => 05448712
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-05
[patent_title] => 'Circuitry and method for programming and erasing a non-volatile semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 8/201044
[patent_app_country] => US
[patent_app_date] => 1994-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 9414
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 288
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/448/05448712.pdf
[firstpage_image] =>[orig_patent_app_number] => 201044
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/201044 | Circuitry and method for programming and erasing a non-volatile semiconductor memory | Feb 23, 1994 | Issued |
| 08/199370 | CIRCUIT AND METHOD FOR LEARNING ATTRIBUTES OF COMPUTER MEMORY | Feb 16, 1994 | Abandoned |
| 08/197364 | CIRCUITRY AND METHOD FOR SELECTIVELY PROTECTING THE INTEGRITY OF DATA STORED WITHIN A RANGE OF ADDRESSES WITHIN A NON-VOLATILE SEMICONDUCTOR MEMORY | Feb 14, 1994 | Abandoned |
