Search

Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
08/195827 VERSATILE CACHE MEMORY Feb 9, 1994 Abandoned
08/194289 SYSTEM AND METHOD FOR PROTECTING INFORMATION STORED ON PHYSICAL MEDIA Feb 8, 1994 Abandoned
Array ( [id] => 3523962 [patent_doc_number] => 05564030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Circuit and method for detecting segment limit errors for code fetches' [patent_app_type] => 1 [patent_app_number] => 8/193289 [patent_app_country] => US [patent_app_date] => 1994-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4788 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/564/05564030.pdf [firstpage_image] =>[orig_patent_app_number] => 193289 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/193289
Circuit and method for detecting segment limit errors for code fetches Feb 7, 1994 Issued
Array ( [id] => 3016461 [patent_doc_number] => 05375214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-20 [patent_title] => 'Single translation mechanism for virtual storage dynamic address translation with non-uniform page sizes' [patent_app_type] => 1 [patent_app_number] => 8/192768 [patent_app_country] => US [patent_app_date] => 1994-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2882 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/375/05375214.pdf [firstpage_image] =>[orig_patent_app_number] => 192768 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/192768
Single translation mechanism for virtual storage dynamic address translation with non-uniform page sizes Feb 6, 1994 Issued
08/191888 DATA PROCESSOR WITH BRANCH TARGET ADDRESS CACHE AND METHOD OF OPERATION Feb 3, 1994 Abandoned
Array ( [id] => 3896358 [patent_doc_number] => 05894440 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Semiconductor memory device and data transferring structure and method therein' [patent_app_type] => 1 [patent_app_number] => 8/189276 [patent_app_country] => US [patent_app_date] => 1994-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7384 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894440.pdf [firstpage_image] =>[orig_patent_app_number] => 189276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/189276
Semiconductor memory device and data transferring structure and method therein Jan 30, 1994 Issued
08/186215 MULTIPLE INPUT BUFFERS FOR ADDRESS BITS Jan 23, 1994 Abandoned
08/184529 DATA PROCESSOR WITH AN EFFICIENT BIT MOVE CAPABILITY AND METHOD THEREFOR Jan 20, 1994 Abandoned
Array ( [id] => 3432849 [patent_doc_number] => 05422841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Semiconductor memory device having reverse base current bipolar transistor-field effect transistor memory cell' [patent_app_type] => 1 [patent_app_number] => 8/170434 [patent_app_country] => US [patent_app_date] => 1993-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5936 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422841.pdf [firstpage_image] =>[orig_patent_app_number] => 170434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/170434
Semiconductor memory device having reverse base current bipolar transistor-field effect transistor memory cell Dec 19, 1993 Issued
08/168827 CONFLICT RESOLUTION IN INTERLEAVED MEMORY SYSTEMS WITH MULTIPLE PARALLEL ACCESSES Dec 14, 1993 Abandoned
Array ( [id] => 3575821 [patent_doc_number] => 05526504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Variable page size translation lookaside buffer' [patent_app_type] => 1 [patent_app_number] => 8/168822 [patent_app_country] => US [patent_app_date] => 1993-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6394 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/526/05526504.pdf [firstpage_image] =>[orig_patent_app_number] => 168822 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/168822
Variable page size translation lookaside buffer Dec 14, 1993 Issued
Array ( [id] => 3761978 [patent_doc_number] => 05802341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method for the dynamic allocation of page sizes in virtual memory' [patent_app_type] => 1 [patent_app_number] => 8/166451 [patent_app_country] => US [patent_app_date] => 1993-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3871 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802341.pdf [firstpage_image] =>[orig_patent_app_number] => 166451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/166451
Method for the dynamic allocation of page sizes in virtual memory Dec 12, 1993 Issued
Array ( [id] => 3700161 [patent_doc_number] => 05696922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Recursive address centrifuge for distributed memory massively parallel processing systems' [patent_app_type] => 1 [patent_app_number] => 8/165388 [patent_app_country] => US [patent_app_date] => 1993-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 12708 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696922.pdf [firstpage_image] =>[orig_patent_app_number] => 165388 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/165388
Recursive address centrifuge for distributed memory massively parallel processing systems Dec 9, 1993 Issued
Array ( [id] => 3897901 [patent_doc_number] => 05765181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'System and method of addressing distributed memory within a massively parallel processing system' [patent_app_type] => 1 [patent_app_number] => 8/165118 [patent_app_country] => US [patent_app_date] => 1993-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 12863 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765181.pdf [firstpage_image] =>[orig_patent_app_number] => 165118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/165118
System and method of addressing distributed memory within a massively parallel processing system Dec 9, 1993 Issued
Array ( [id] => 3844107 [patent_doc_number] => 05712999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Address generator employing selective merge of two independent addresses' [patent_app_type] => 1 [patent_app_number] => 8/160114 [patent_app_country] => US [patent_app_date] => 1993-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 70 [patent_no_of_words] => 99259 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712999.pdf [firstpage_image] =>[orig_patent_app_number] => 160114 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/160114
Address generator employing selective merge of two independent addresses Nov 29, 1993 Issued
08/158648 CACHE ADDRESSING MECHANISM THAT ADAPTS MULTI-DIMENSIONAL ADDRESSING TOPOLOGY Nov 28, 1993 Abandoned
Array ( [id] => 4209066 [patent_doc_number] => 06154827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Data processor capable of high speed accessing' [patent_app_type] => 1 [patent_app_number] => 8/154695 [patent_app_country] => US [patent_app_date] => 1993-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 13 [patent_no_of_words] => 4693 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154827.pdf [firstpage_image] =>[orig_patent_app_number] => 154695 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/154695
Data processor capable of high speed accessing Nov 18, 1993 Issued
Array ( [id] => 3085004 [patent_doc_number] => 05337416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-09 [patent_title] => 'Apparatus for managing page zero accesses in a multi-processor data processing system' [patent_app_type] => 1 [patent_app_number] => 8/154675 [patent_app_country] => US [patent_app_date] => 1993-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2417 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/337/05337416.pdf [firstpage_image] =>[orig_patent_app_number] => 154675 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/154675
Apparatus for managing page zero accesses in a multi-processor data processing system Nov 17, 1993 Issued
Array ( [id] => 3701317 [patent_doc_number] => 05664149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol' [patent_app_type] => 1 [patent_app_number] => 8/151489 [patent_app_country] => US [patent_app_date] => 1993-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7573 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664149.pdf [firstpage_image] =>[orig_patent_app_number] => 151489 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/151489
Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol Nov 11, 1993 Issued
Array ( [id] => 4170108 [patent_doc_number] => 06108254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Dynamic random access memory having continuous data line equalization except at address transition during data reading' [patent_app_type] => 1 [patent_app_number] => 8/150782 [patent_app_country] => US [patent_app_date] => 1993-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4619 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108254.pdf [firstpage_image] =>[orig_patent_app_number] => 150782 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/150782
Dynamic random access memory having continuous data line equalization except at address transition during data reading Nov 11, 1993 Issued
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