Search

Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3497701 [patent_doc_number] => 05475643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Semiconductor signal line system with crosstalk reduction' [patent_app_type] => 1 [patent_app_number] => 8/150243 [patent_app_country] => US [patent_app_date] => 1993-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2166 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/475/05475643.pdf [firstpage_image] =>[orig_patent_app_number] => 150243 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/150243
Semiconductor signal line system with crosstalk reduction Nov 8, 1993 Issued
Array ( [id] => 3667466 [patent_doc_number] => 05623636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Data processing system and method for providing memory access protection using transparent translation registers and default attribute bits' [patent_app_type] => 1 [patent_app_number] => 8/149496 [patent_app_country] => US [patent_app_date] => 1993-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4477 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623636.pdf [firstpage_image] =>[orig_patent_app_number] => 149496 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/149496
Data processing system and method for providing memory access protection using transparent translation registers and default attribute bits Nov 8, 1993 Issued
Array ( [id] => 3601017 [patent_doc_number] => 05550996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'ROM burst transfer continuous read-out extension method and a microcomputer system with a built-in ROM using this method' [patent_app_type] => 1 [patent_app_number] => 8/143779 [patent_app_country] => US [patent_app_date] => 1993-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3816 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550996.pdf [firstpage_image] =>[orig_patent_app_number] => 143779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/143779
ROM burst transfer continuous read-out extension method and a microcomputer system with a built-in ROM using this method Oct 31, 1993 Issued
Array ( [id] => 3622744 [patent_doc_number] => 05566124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Semiconductor memory device capable of reading required data signal at designated address interval and method of operation thereof' [patent_app_type] => 1 [patent_app_number] => 8/141716 [patent_app_country] => US [patent_app_date] => 1993-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 5721 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/566/05566124.pdf [firstpage_image] =>[orig_patent_app_number] => 141716 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/141716
Semiconductor memory device capable of reading required data signal at designated address interval and method of operation thereof Oct 26, 1993 Issued
Array ( [id] => 3603506 [patent_doc_number] => 05586281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Data driven type information processing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/141207 [patent_app_country] => US [patent_app_date] => 1993-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 8915 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586281.pdf [firstpage_image] =>[orig_patent_app_number] => 141207 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/141207
Data driven type information processing apparatus Oct 25, 1993 Issued
Array ( [id] => 3488437 [patent_doc_number] => 05432923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Memory access control device capable of carrying out data transfer between main memory and expanded memory with simple control' [patent_app_type] => 1 [patent_app_number] => 8/134874 [patent_app_country] => US [patent_app_date] => 1993-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5305 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 522 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432923.pdf [firstpage_image] =>[orig_patent_app_number] => 134874 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/134874
Memory access control device capable of carrying out data transfer between main memory and expanded memory with simple control Oct 11, 1993 Issued
Array ( [id] => 3603537 [patent_doc_number] => 05586283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Method and apparatus for the reduction of tablewalk latencies in a translation look aside buffer' [patent_app_type] => 1 [patent_app_number] => 8/132796 [patent_app_country] => US [patent_app_date] => 1993-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4407 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586283.pdf [firstpage_image] =>[orig_patent_app_number] => 132796 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/132796
Method and apparatus for the reduction of tablewalk latencies in a translation look aside buffer Oct 6, 1993 Issued
Array ( [id] => 3437807 [patent_doc_number] => 05404477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Extended memory address conversion and data transfer control system' [patent_app_type] => 1 [patent_app_number] => 8/131876 [patent_app_country] => US [patent_app_date] => 1993-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2396 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404477.pdf [firstpage_image] =>[orig_patent_app_number] => 131876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/131876
Extended memory address conversion and data transfer control system Oct 4, 1993 Issued
08/130060 DYNAMIC NON-COHERENT CACHE MEMORY RESIZING MECHANISM Sep 29, 1993 Abandoned
08/125992 METHOD AND APPARATUS TO ELIMINATE REDUNDANT MAPPING IN A TLB UTILIZING VARIABLE SIZED PAGES Sep 22, 1993 Abandoned
Array ( [id] => 3526361 [patent_doc_number] => 05513333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Circuitry and method for programming and erasing a non-volatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/100508 [patent_app_country] => US [patent_app_date] => 1993-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9473 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/513/05513333.pdf [firstpage_image] =>[orig_patent_app_number] => 100508 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/100508
Circuitry and method for programming and erasing a non-volatile semiconductor memory Sep 14, 1993 Issued
08/119794 A VERY LARGE SCALE INTEGRATED CIRCUIT MEMORY DEVICE HAVING A TWO STAGE REDUNDANCY DECODING CIRCUIT Sep 9, 1993 Abandoned
Array ( [id] => 3025433 [patent_doc_number] => 05341329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Nonvolatile semiconductor memory device capable of preventing read error caused by overerase state and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/118285 [patent_app_country] => US [patent_app_date] => 1993-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6506 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341329.pdf [firstpage_image] =>[orig_patent_app_number] => 118285 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/118285
Nonvolatile semiconductor memory device capable of preventing read error caused by overerase state and method therefor Sep 8, 1993 Issued
08/112203 DATA TRANSFER USING LOCAL AND GLOBAL ADDRESS TRANSLATION AND AUTHORIZATION Aug 25, 1993 Abandoned
Array ( [id] => 3497426 [patent_doc_number] => 05426750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Translation lookaside buffer apparatus and method with input/output entries, page table entries and page table pointers' [patent_app_type] => 1 [patent_app_number] => 8/107220 [patent_app_country] => US [patent_app_date] => 1993-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5955 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426750.pdf [firstpage_image] =>[orig_patent_app_number] => 107220 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/107220
Translation lookaside buffer apparatus and method with input/output entries, page table entries and page table pointers Aug 15, 1993 Issued
08/100742 METHOD AND APPARATUS FOR TRANSPARENTLY COMPRESSING DATA IN A PRIMARY STORAGE DEVICE Jul 29, 1993 Pending
Array ( [id] => 3012572 [patent_doc_number] => 05371703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Single-bit output type memory including bipolar selection transistors' [patent_app_type] => 1 [patent_app_number] => 8/094359 [patent_app_country] => US [patent_app_date] => 1993-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5694 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 640 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371703.pdf [firstpage_image] =>[orig_patent_app_number] => 094359 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/094359
Single-bit output type memory including bipolar selection transistors Jul 20, 1993 Issued
Array ( [id] => 3672527 [patent_doc_number] => 05592638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Storage region assignment method in a logically partitioned environment' [patent_app_type] => 1 [patent_app_number] => 8/090953 [patent_app_country] => US [patent_app_date] => 1993-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4261 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592638.pdf [firstpage_image] =>[orig_patent_app_number] => 090953 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/090953
Storage region assignment method in a logically partitioned environment Jul 12, 1993 Issued
08/086454 SYSTEM FOR CONTROLLING A WRITE OPERATION INVOLVING DATA HELD IN A WRITE CACHE Jun 30, 1993 Pending
Array ( [id] => 3604432 [patent_doc_number] => 05568620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Method and apparatus for performing bus transactions in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/085541 [patent_app_country] => US [patent_app_date] => 1993-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9450 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568620.pdf [firstpage_image] =>[orig_patent_app_number] => 085541 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/085541
Method and apparatus for performing bus transactions in a computer system Jun 29, 1993 Issued
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