| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3453296
[patent_doc_number] => 05398326
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-14
[patent_title] => 'Method for data communication'
[patent_app_type] => 1
[patent_app_number] => 8/019932
[patent_app_country] => US
[patent_app_date] => 1993-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 48
[patent_no_of_words] => 22118
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 477
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/398/05398326.pdf
[firstpage_image] =>[orig_patent_app_number] => 019932
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/019932 | Method for data communication | Feb 18, 1993 | Issued |
Array
(
[id] => 3681685
[patent_doc_number] => 05600813
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Method of and circuit for generating zigzag addresses'
[patent_app_type] => 1
[patent_app_number] => 8/015374
[patent_app_country] => US
[patent_app_date] => 1993-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 62
[patent_figures_cnt] => 64
[patent_no_of_words] => 15280
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600813.pdf
[firstpage_image] =>[orig_patent_app_number] => 015374
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/015374 | Method of and circuit for generating zigzag addresses | Feb 8, 1993 | Issued |
| 08/014977 | MULTI-ZONE RELOCATION FACILITY COMPUTER MEMORY SYSTEM | Feb 7, 1993 | Abandoned |
Array
(
[id] => 3647702
[patent_doc_number] => 05611064
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Virtual memory system'
[patent_app_type] => 1
[patent_app_number] => 8/034838
[patent_app_country] => US
[patent_app_date] => 1993-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 74
[patent_no_of_words] => 24392
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/611/05611064.pdf
[firstpage_image] =>[orig_patent_app_number] => 034838
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/034838 | Virtual memory system | Jan 31, 1993 | Issued |
Array
(
[id] => 3700967
[patent_doc_number] => 05644748
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-01
[patent_title] => 'Processor system including an index buffer circuit and a translation look-aside buffer control circuit for processor-to-processor interfacing'
[patent_app_type] => 1
[patent_app_number] => 8/011761
[patent_app_country] => US
[patent_app_date] => 1993-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 27
[patent_no_of_words] => 11980
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 385
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/644/05644748.pdf
[firstpage_image] =>[orig_patent_app_number] => 011761
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/011761 | Processor system including an index buffer circuit and a translation look-aside buffer control circuit for processor-to-processor interfacing | Jan 31, 1993 | Issued |
Array
(
[id] => 2945042
[patent_doc_number] => 05247475
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-21
[patent_title] => 'Superconducting memory circuit and method of storing information in the same by generating and terminating a persistent current'
[patent_app_type] => 1
[patent_app_number] => 8/002115
[patent_app_country] => US
[patent_app_date] => 1993-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4892
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 480
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/247/05247475.pdf
[firstpage_image] =>[orig_patent_app_number] => 002115
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/002115 | Superconducting memory circuit and method of storing information in the same by generating and terminating a persistent current | Jan 3, 1993 | Issued |
Array
(
[id] => 3569643
[patent_doc_number] => 05544338
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Apparatus and method for raster generation from sparse area array output'
[patent_app_type] => 1
[patent_app_number] => 7/999049
[patent_app_country] => US
[patent_app_date] => 1992-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 10444
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/544/05544338.pdf
[firstpage_image] =>[orig_patent_app_number] => 999049
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/999049 | Apparatus and method for raster generation from sparse area array output | Dec 30, 1992 | Issued |
| 07/998978 | COMMUNICATION MODULE | Dec 29, 1992 | Abandoned |
Array
(
[id] => 3588900
[patent_doc_number] => 05524225
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'Cache system and method for providing software controlled writeback'
[patent_app_type] => 1
[patent_app_number] => 7/993095
[patent_app_country] => US
[patent_app_date] => 1992-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3541
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/524/05524225.pdf
[firstpage_image] =>[orig_patent_app_number] => 993095
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/993095 | Cache system and method for providing software controlled writeback | Dec 17, 1992 | Issued |
Array
(
[id] => 3569147
[patent_doc_number] => 05502828
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-26
[patent_title] => 'Reducing memory access in a multi-cache multiprocessing environment with each cache mapped into different areas of main memory to avoid contention'
[patent_app_type] => 1
[patent_app_number] => 7/993005
[patent_app_country] => US
[patent_app_date] => 1992-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2099
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/502/05502828.pdf
[firstpage_image] =>[orig_patent_app_number] => 993005
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/993005 | Reducing memory access in a multi-cache multiprocessing environment with each cache mapped into different areas of main memory to avoid contention | Dec 17, 1992 | Issued |
| 07/997142 | SEMICONDUCTOR MEMORY DEVICE WHICH IS CAPABLE OF CORRECTING A BIT FAILURE | Dec 7, 1992 | Abandoned |
Array
(
[id] => 2947093
[patent_doc_number] => 05230070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-20
[patent_title] => 'Access authorization table for multi-processor caches'
[patent_app_type] => 1
[patent_app_number] => 7/984001
[patent_app_country] => US
[patent_app_date] => 1992-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 7398
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/230/05230070.pdf
[firstpage_image] =>[orig_patent_app_number] => 984001
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/984001 | Access authorization table for multi-processor caches | Nov 30, 1992 | Issued |
Array
(
[id] => 3118431
[patent_doc_number] => 05408435
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-18
[patent_title] => 'Semiconductor memory with inhibited test mode entry during power-up'
[patent_app_type] => 1
[patent_app_number] => 7/984233
[patent_app_country] => US
[patent_app_date] => 1992-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 23692
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/408/05408435.pdf
[firstpage_image] =>[orig_patent_app_number] => 984233
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/984233 | Semiconductor memory with inhibited test mode entry during power-up | Nov 19, 1992 | Issued |
| 07/977226 | CONCURRENT CACHE LINE REPLACEMENT METHOD AND APPARATUS IN MICROPROCESSOR SYSTEM WITH WRITE-BACK CACHE MEMORY | Nov 15, 1992 | Abandoned |
| 07/977228 | PSEUDO-CONCURRENT ACCESS TO A CACHED SHARED RESOURCE | Nov 15, 1992 | Abandoned |
Array
(
[id] => 3625476
[patent_doc_number] => 05566309
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Variable memory boundaries between external and internal memories for single-chip microcomputer'
[patent_app_type] => 1
[patent_app_number] => 7/976218
[patent_app_country] => US
[patent_app_date] => 1992-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4057
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 323
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/566/05566309.pdf
[firstpage_image] =>[orig_patent_app_number] => 976218
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/976218 | Variable memory boundaries between external and internal memories for single-chip microcomputer | Nov 12, 1992 | Issued |
Array
(
[id] => 3566407
[patent_doc_number] => 05519841
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-21
[patent_title] => 'Multi instruction register mapper'
[patent_app_type] => 1
[patent_app_number] => 7/974776
[patent_app_country] => US
[patent_app_date] => 1992-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 31628
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/519/05519841.pdf
[firstpage_image] =>[orig_patent_app_number] => 974776
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/974776 | Multi instruction register mapper | Nov 11, 1992 | Issued |
| 07/971748 | MIL-STD-1553 INTERFACE DEVICE HAVING A BUS CONTROLLER OPCODE SET | Nov 3, 1992 | Abandoned |
Array
(
[id] => 3564464
[patent_doc_number] => 05493660
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Software assisted hardware TLB miss handler'
[patent_app_type] => 1
[patent_app_number] => 7/957345
[patent_app_country] => US
[patent_app_date] => 1992-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6938
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/493/05493660.pdf
[firstpage_image] =>[orig_patent_app_number] => 957345
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/957345 | Software assisted hardware TLB miss handler | Oct 5, 1992 | Issued |
Array
(
[id] => 3566078
[patent_doc_number] => 05574877
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'TLB with two physical pages per virtual tag'
[patent_app_type] => 1
[patent_app_number] => 7/951471
[patent_app_country] => US
[patent_app_date] => 1992-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2071
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/574/05574877.pdf
[firstpage_image] =>[orig_patent_app_number] => 951471
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/951471 | TLB with two physical pages per virtual tag | Sep 24, 1992 | Issued |