Telly D. Green

Array ( [id] => 3564518 [patent_doc_number] => 05493663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-20 [patent_title] => 'Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses' [patent_app_type] => 1 [patent_app_number] => 7/872733 [patent_app_country] => US [patent_app_date] => 1992-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5038 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/493/05493663.pdf [firstpage_image] =>[orig_patent_app_number] => 872733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2833904 [patent_doc_number] => 05170372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-08 [patent_title] => 'Memory device having bit lines over a field oxide' [patent_app_type] => 1 [patent_app_number] => 7/870158 [patent_app_country] => US [patent_app_date] => 1992-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1493 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/170/05170372.pdf [firstpage_image] =>[orig_patent_app_number] => 870158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4034385 [patent_doc_number] => 05926412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Ferroelectric memory structure' [patent_app_type] => 1 [patent_app_number] => 7/864152 [patent_app_country] => US [patent_app_date] => 1992-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5860 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926412.pdf [firstpage_image] =>[orig_patent_app_number] => 864152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3096485 [patent_doc_number] => 05285421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Scheme for eliminating page boundary limitation on initial access of a serial contiguous access memory' [patent_app_type] => 1 [patent_app_number] => 7/865812 [patent_app_country] => US [patent_app_date] => 1992-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2897 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/285/05285421.pdf [firstpage_image] =>[orig_patent_app_number] => 865812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2922668 [patent_doc_number] => 05237534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-17 [patent_title] => 'Data sense circuit for a semiconductor nonvolatile memory device' [patent_app_type] => 1 [patent_app_number] => 7/854793 [patent_app_country] => US [patent_app_date] => 1992-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4657 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 565 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/237/05237534.pdf [firstpage_image] =>[orig_patent_app_number] => 854793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3600846 [patent_doc_number] => 05517599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Data recording system and method having logical overrecording capability' [patent_app_type] => 1 [patent_app_number] => 7/843454 [patent_app_country] => US [patent_app_date] => 1992-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 19536 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517599.pdf [firstpage_image] =>[orig_patent_app_number] => 843454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3435481 [patent_doc_number] => 05423016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Block buffer for instruction/operand caches' [patent_app_type] => 1 [patent_app_number] => 7/840464 [patent_app_country] => US [patent_app_date] => 1992-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4897 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/423/05423016.pdf [firstpage_image] =>[orig_patent_app_number] => 840464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3086016 [patent_doc_number] => 05323347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-21 [patent_title] => 'Semiconductor memory device storing two types of binary number data and method of operating the same' [patent_app_type] => 1 [patent_app_number] => 7/832570 [patent_app_country] => US [patent_app_date] => 1992-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7138 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/323/05323347.pdf [firstpage_image] =>[orig_patent_app_number] => 832570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3047412 [patent_doc_number] => 05301163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Memory selection/deselection circuitry having a wordline discharge circuit' [patent_app_type] => 1 [patent_app_number] => 7/830768 [patent_app_country] => US [patent_app_date] => 1992-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3043 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/301/05301163.pdf [firstpage_image] =>[orig_patent_app_number] => 830768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2814225 [patent_doc_number] => 05146427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-08 [patent_title] => 'High speed semiconductor memory having a direct-bypass signal path' [patent_app_type] => 1 [patent_app_number] => 7/825782 [patent_app_country] => US [patent_app_date] => 1992-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4875 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/146/05146427.pdf [firstpage_image] =>[orig_patent_app_number] => 825782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2905256 [patent_doc_number] => 05184321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-02 [patent_title] => 'Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement' [patent_app_type] => 1 [patent_app_number] => 7/821875 [patent_app_country] => US [patent_app_date] => 1992-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 6325 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/184/05184321.pdf [firstpage_image] =>[orig_patent_app_number] => 821875 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2973787 [patent_doc_number] => 05265055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Semiconductor memory having redundancy circuit' [patent_app_type] => 1 [patent_app_number] => 7/818434 [patent_app_country] => US [patent_app_date] => 1991-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 36 [patent_no_of_words] => 16789 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/265/05265055.pdf [firstpage_image] =>[orig_patent_app_number] => 818434 [rel_patent_id] =>[rel_patent_doc_number] =>)