Search

Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2977768 [patent_doc_number] => 05202852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Programmable read only memory card with improved buffer circuit' [patent_app_type] => 1 [patent_app_number] => 7/713560 [patent_app_country] => US [patent_app_date] => 1991-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2533 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 445 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202852.pdf [firstpage_image] =>[orig_patent_app_number] => 713560 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/713560
Programmable read only memory card with improved buffer circuit Jun 9, 1991 Issued
Array ( [id] => 2851099 [patent_doc_number] => 05172340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-15 [patent_title] => 'Double stage bipolar sense amplifier for BICMOS SRAMS with a common base amplifier in the final stage' [patent_app_type] => 1 [patent_app_number] => 7/714319 [patent_app_country] => US [patent_app_date] => 1991-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4506 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 482 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/172/05172340.pdf [firstpage_image] =>[orig_patent_app_number] => 714319 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/714319
Double stage bipolar sense amplifier for BICMOS SRAMS with a common base amplifier in the final stage Jun 9, 1991 Issued
07/709873 DYNAMIC RANDOM ACCESS MEMORY HAVING SYNCHRONOUS DATA TRANSFER MEANS Jun 3, 1991 Abandoned
Array ( [id] => 2983456 [patent_doc_number] => 05195053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-16 [patent_title] => 'Semiconductor memory device wired to accommodate increased capacity without increasing the size of the semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 7/704916 [patent_app_country] => US [patent_app_date] => 1991-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4637 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/195/05195053.pdf [firstpage_image] =>[orig_patent_app_number] => 704916 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/704916
Semiconductor memory device wired to accommodate increased capacity without increasing the size of the semiconductor memory device May 21, 1991 Issued
Array ( [id] => 2931729 [patent_doc_number] => 05200924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Bit line discharge and sense circuit' [patent_app_type] => 1 [patent_app_number] => 7/704675 [patent_app_country] => US [patent_app_date] => 1991-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2142 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/200/05200924.pdf [firstpage_image] =>[orig_patent_app_number] => 704675 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/704675
Bit line discharge and sense circuit May 20, 1991 Issued
07/703077 REDUNDANCY ARCHITECTURE AND METHOD FOR BLOCK WRITE ACCESS CYCLES PERMITTING DEFECTIVE MEMORY LINE REPLACEMENT May 19, 1991 Abandoned
07/698721 CIRCUITRY AND METHOD FOR SELECTIVELY PROTECTING THE INTEGRITY OF DATA STORED WITHIN A RANGE OF ADDRESSES WITHIN A NON-VOLATILE SEMICONDUCTOR MEMORY May 9, 1991 Abandoned
07/698514 SYSTEM FOR REMAPPING PHYSICAL MEMORY May 9, 1991 Abandoned
Array ( [id] => 3028357 [patent_doc_number] => 05341485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Multiple virtual address translation per computer cycle' [patent_app_type] => 1 [patent_app_number] => 7/697168 [patent_app_country] => US [patent_app_date] => 1991-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 4040 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341485.pdf [firstpage_image] =>[orig_patent_app_number] => 697168 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/697168
Multiple virtual address translation per computer cycle May 6, 1991 Issued
Array ( [id] => 2904085 [patent_doc_number] => 05177704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-01-05 [patent_title] => 'Matrix transpose memory device' [patent_app_type] => 1 [patent_app_number] => 7/691793 [patent_app_country] => US [patent_app_date] => 1991-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4212 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/177/05177704.pdf [firstpage_image] =>[orig_patent_app_number] => 691793 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/691793
Matrix transpose memory device Apr 25, 1991 Issued
Array ( [id] => 3111078 [patent_doc_number] => 05319759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-07 [patent_title] => 'Burst address sequence generator' [patent_app_type] => 1 [patent_app_number] => 7/689309 [patent_app_country] => US [patent_app_date] => 1991-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2882 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/319/05319759.pdf [firstpage_image] =>[orig_patent_app_number] => 689309 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/689309
Burst address sequence generator Apr 21, 1991 Issued
Array ( [id] => 3093784 [patent_doc_number] => 05321824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-14 [patent_title] => 'Accessing last recorded data in a continuation chain' [patent_app_type] => 1 [patent_app_number] => 7/688228 [patent_app_country] => US [patent_app_date] => 1991-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3322 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/321/05321824.pdf [firstpage_image] =>[orig_patent_app_number] => 688228 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/688228
Accessing last recorded data in a continuation chain Apr 21, 1991 Issued
Array ( [id] => 2810342 [patent_doc_number] => 05140552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Semiconductor memory device having a volatile memory device and a non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 7/687243 [patent_app_country] => US [patent_app_date] => 1991-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4438 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140552.pdf [firstpage_image] =>[orig_patent_app_number] => 687243 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/687243
Semiconductor memory device having a volatile memory device and a non-volatile memory device Apr 17, 1991 Issued
Array ( [id] => 2985497 [patent_doc_number] => 05208783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-04 [patent_title] => 'Memory unit delay-compensating circuit' [patent_app_type] => 1 [patent_app_number] => 7/684735 [patent_app_country] => US [patent_app_date] => 1991-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3544 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/208/05208783.pdf [firstpage_image] =>[orig_patent_app_number] => 684735 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/684735
Memory unit delay-compensating circuit Apr 14, 1991 Issued
Array ( [id] => 3488408 [patent_doc_number] => 05432920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-11 [patent_title] => 'Store control method with hierarchic priority scheme for computer system' [patent_app_type] => 1 [patent_app_number] => 7/685450 [patent_app_country] => US [patent_app_date] => 1991-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 25290 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/432/05432920.pdf [firstpage_image] =>[orig_patent_app_number] => 685450 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/685450
Store control method with hierarchic priority scheme for computer system Apr 14, 1991 Issued
07/679709 HYBRID CACHE AND METHOD FOR ACCESSING SAME Apr 2, 1991 Abandoned
Array ( [id] => 3085980 [patent_doc_number] => 05323345 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-21 [patent_title] => 'Semiconductor memory device having read/write circuitry' [patent_app_type] => 1 [patent_app_number] => 7/676073 [patent_app_country] => US [patent_app_date] => 1991-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6880 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/323/05323345.pdf [firstpage_image] =>[orig_patent_app_number] => 676073 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/676073
Semiconductor memory device having read/write circuitry Mar 26, 1991 Issued
Array ( [id] => 3497383 [patent_doc_number] => 05426747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Method and apparatus for virtual memory mapping and transaction management in an object-oriented database system' [patent_app_type] => 1 [patent_app_number] => 7/674874 [patent_app_country] => US [patent_app_date] => 1991-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 14981 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426747.pdf [firstpage_image] =>[orig_patent_app_number] => 674874 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/674874
Method and apparatus for virtual memory mapping and transaction management in an object-oriented database system Mar 21, 1991 Issued
07/668642 SINGLE TRANSLATION MECHANISM FOR VIRTUAL STORAGE DYNAMIC ADDRESS TRANSLATION WITH NON-UNIFORM PAGE SIZES Mar 12, 1991 Abandoned
07/666479 METHOD OF DRIVING DEVICE HAVING MIM STRUCTURE Mar 5, 1991 Abandoned
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