Search

Telly D. Green

Examiner (ID: 7164, Phone: (571)270-3204 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2809, 2822
Total Applications
1671
Issued Applications
1353
Pending Applications
119
Abandoned Applications
249

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2880654 [patent_doc_number] => 05163023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Memory circuit capable of replacing a faulty column with a spare column' [patent_app_type] => 1 [patent_app_number] => 7/602369 [patent_app_country] => US [patent_app_date] => 1990-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4532 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 590 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/163/05163023.pdf [firstpage_image] =>[orig_patent_app_number] => 602369 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/602369
Memory circuit capable of replacing a faulty column with a spare column Oct 22, 1990 Issued
07/590980 MEMORY WITH A COMBINED GLOBAL DATA LINE LOAD AND MULTIPLEXER Sep 30, 1990 Abandoned
Array ( [id] => 2840517 [patent_doc_number] => 05128894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Multi-value memory cell using resonant tunnelling diodes' [patent_app_type] => 1 [patent_app_number] => 7/590139 [patent_app_country] => US [patent_app_date] => 1990-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 3192 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/128/05128894.pdf [firstpage_image] =>[orig_patent_app_number] => 590139 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/590139
Multi-value memory cell using resonant tunnelling diodes Sep 27, 1990 Issued
Array ( [id] => 2905017 [patent_doc_number] => 05241494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-31 [patent_title] => 'Integrated circuit system for analog signal recording and playback' [patent_app_type] => 1 [patent_app_number] => 7/588949 [patent_app_country] => US [patent_app_date] => 1990-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 13356 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 510 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/241/05241494.pdf [firstpage_image] =>[orig_patent_app_number] => 588949 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/588949
Integrated circuit system for analog signal recording and playback Sep 25, 1990 Issued
Array ( [id] => 2847452 [patent_doc_number] => 05121358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Semiconductor memory with power-on reset controlled latched row line repeaters' [patent_app_type] => 1 [patent_app_number] => 7/588609 [patent_app_country] => US [patent_app_date] => 1990-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 12838 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121358.pdf [firstpage_image] =>[orig_patent_app_number] => 588609 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/588609
Semiconductor memory with power-on reset controlled latched row line repeaters Sep 25, 1990 Issued
Array ( [id] => 2840576 [patent_doc_number] => 05128897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-07 [patent_title] => 'Semiconductor memory having improved latched repeaters for memory row line selection' [patent_app_type] => 1 [patent_app_number] => 7/588577 [patent_app_country] => US [patent_app_date] => 1990-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 9250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/128/05128897.pdf [firstpage_image] =>[orig_patent_app_number] => 588577 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/588577
Semiconductor memory having improved latched repeaters for memory row line selection Sep 25, 1990 Issued
Array ( [id] => 2813506 [patent_doc_number] => 05124951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-23 [patent_title] => 'Semiconductor memory with sequenced latched row line repeaters' [patent_app_type] => 1 [patent_app_number] => 7/588600 [patent_app_country] => US [patent_app_date] => 1990-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 9406 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/124/05124951.pdf [firstpage_image] =>[orig_patent_app_number] => 588600 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/588600
Semiconductor memory with sequenced latched row line repeaters Sep 25, 1990 Issued
Array ( [id] => 2889208 [patent_doc_number] => 05119340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-02 [patent_title] => 'Semiconductor memory having latched repeaters for memory row line selection' [patent_app_type] => 1 [patent_app_number] => 7/588601 [patent_app_country] => US [patent_app_date] => 1990-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 9183 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/119/05119340.pdf [firstpage_image] =>[orig_patent_app_number] => 588601 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/588601
Semiconductor memory having latched repeaters for memory row line selection Sep 25, 1990 Issued
Array ( [id] => 2743861 [patent_doc_number] => 05051952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Semiconductor memory device having capacitors through which data read/write is carried out' [patent_app_type] => 1 [patent_app_number] => 7/588629 [patent_app_country] => US [patent_app_date] => 1990-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 37 [patent_no_of_words] => 7901 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051952.pdf [firstpage_image] =>[orig_patent_app_number] => 588629 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/588629
Semiconductor memory device having capacitors through which data read/write is carried out Sep 24, 1990 Issued
Array ( [id] => 2945128 [patent_doc_number] => 05229967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'BICMOS sense circuit for sensing data during a read cycle of a memory' [patent_app_type] => 1 [patent_app_number] => 7/577375 [patent_app_country] => US [patent_app_date] => 1990-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 12608 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229967.pdf [firstpage_image] =>[orig_patent_app_number] => 577375 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/577375
BICMOS sense circuit for sensing data during a read cycle of a memory Sep 3, 1990 Issued
Array ( [id] => 2937729 [patent_doc_number] => 05187683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-16 [patent_title] => 'Method for programming EEPROM memory arrays' [patent_app_type] => 1 [patent_app_number] => 7/576307 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3892 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/187/05187683.pdf [firstpage_image] =>[orig_patent_app_number] => 576307 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/576307
Method for programming EEPROM memory arrays Aug 30, 1990 Issued
Array ( [id] => 2864988 [patent_doc_number] => 05113374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'MOS type semiconductor memory device having a word line resetting circuit' [patent_app_type] => 1 [patent_app_number] => 7/574729 [patent_app_country] => US [patent_app_date] => 1990-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2014 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/113/05113374.pdf [firstpage_image] =>[orig_patent_app_number] => 574729 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/574729
MOS type semiconductor memory device having a word line resetting circuit Aug 29, 1990 Issued
07/573749 SEMICONDUCTOR MEMORY DEVICE Aug 27, 1990 Abandoned
Array ( [id] => 2851081 [patent_doc_number] => 05172339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-15 [patent_title] => 'Semiconductor memory device having error checking and correcting circuit and operating method therefor' [patent_app_type] => 1 [patent_app_number] => 7/570468 [patent_app_country] => US [patent_app_date] => 1990-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5131 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/172/05172339.pdf [firstpage_image] =>[orig_patent_app_number] => 570468 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/570468
Semiconductor memory device having error checking and correcting circuit and operating method therefor Aug 20, 1990 Issued
Array ( [id] => 2944657 [patent_doc_number] => 05197030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-23 [patent_title] => 'Semiconductor memory device having redundant memory cells' [patent_app_type] => 1 [patent_app_number] => 7/570057 [patent_app_country] => US [patent_app_date] => 1990-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2494 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/197/05197030.pdf [firstpage_image] =>[orig_patent_app_number] => 570057 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/570057
Semiconductor memory device having redundant memory cells Aug 19, 1990 Issued
07/570148 SEMICONDUCTOR MEMORY WITH INHIBITED TEST MODE ENTRY DURING POWER-UP Aug 16, 1990 Abandoned
07/568390 MEMORY DEVICE HAVING BIT LINES OVER A FIELD OXIDE S Aug 15, 1990 Abandoned
07/567099 HIGH SPEED SIMICONDUCTOR MEMORY HAVING A DIRECT-BYPASS SIGNAL PATH Aug 13, 1990 Abandoned
Array ( [id] => 2987396 [patent_doc_number] => 05257230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-10-26 [patent_title] => 'Memory device including redundancy cells with programmable fuel elements and process of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 7/565820 [patent_app_country] => US [patent_app_date] => 1990-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3573 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/257/05257230.pdf [firstpage_image] =>[orig_patent_app_number] => 565820 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/565820
Memory device including redundancy cells with programmable fuel elements and process of manufacturing the same Aug 12, 1990 Issued
07/559483 ARITHMETIC AND LOGIC UNITS Jul 29, 1990 Abandoned
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