Search

Teresa M. Arroyo

Examiner (ID: 14033, Phone: (571)272-7260 , Office: P/2829 )

Most Active Art Unit
2826
Art Unit(s)
2822, 2893, 2811, 2829, 2826, 2508, 2503, 2881
Total Applications
998
Issued Applications
712
Pending Applications
86
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7648860 [patent_doc_number] => 20110298129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'STACKED PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/093123 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4646 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20110298129.pdf [firstpage_image] =>[orig_patent_app_number] => 13093123 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093123
Stacked package Apr 24, 2011 Issued
Array ( [id] => 7648861 [patent_doc_number] => 20110298130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'SEMICONDUCTOR DEVICES WITH THROUGH-SILICON VIAS' [patent_app_type] => utility [patent_app_number] => 13/093439 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6121 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20110298130.pdf [firstpage_image] =>[orig_patent_app_number] => 13093439 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093439
SEMICONDUCTOR DEVICES WITH THROUGH-SILICON VIAS Apr 24, 2011 Abandoned
Array ( [id] => 10145016 [patent_doc_number] => 09177828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'External gettering method and device' [patent_app_type] => utility [patent_app_number] => 13/024806 [patent_app_country] => US [patent_app_date] => 2011-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5131 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13024806 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/024806
External gettering method and device Feb 9, 2011 Issued
Array ( [id] => 9996579 [patent_doc_number] => 09041181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Land grid array package capable of decreasing a height difference between a land and a solder resist' [patent_app_type] => utility [patent_app_number] => 13/024785 [patent_app_country] => US [patent_app_date] => 2011-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4132 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13024785 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/024785
Land grid array package capable of decreasing a height difference between a land and a solder resist Feb 9, 2011 Issued
Array ( [id] => 11411690 [patent_doc_number] => 09559001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Chip package and method for forming the same' [patent_app_type] => utility [patent_app_number] => 13/024156 [patent_app_country] => US [patent_app_date] => 2011-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 6750 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13024156 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/024156
Chip package and method for forming the same Feb 8, 2011 Issued
Array ( [id] => 6161393 [patent_doc_number] => 20110193215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/023565 [patent_app_country] => US [patent_app_date] => 2011-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5895 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20110193215.pdf [firstpage_image] =>[orig_patent_app_number] => 13023565 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/023565
SEMICONDUCTOR PACKAGE Feb 8, 2011 Abandoned
Array ( [id] => 8333256 [patent_doc_number] => 20120199960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'WIRE BONDING FOR INTERCONNECTION BETWEEN INTERPOSER AND FLIP CHIP DIE' [patent_app_type] => utility [patent_app_number] => 13/022146 [patent_app_country] => US [patent_app_date] => 2011-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13022146 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/022146
WIRE BONDING FOR INTERCONNECTION BETWEEN INTERPOSER AND FLIP CHIP DIE Feb 6, 2011 Abandoned
Array ( [id] => 8560138 [patent_doc_number] => 08334201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-18 [patent_title] => 'Semiconductor device and inspection method therefor' [patent_app_type] => utility [patent_app_number] => 12/929631 [patent_app_country] => US [patent_app_date] => 2011-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5238 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12929631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/929631
Semiconductor device and inspection method therefor Feb 3, 2011 Issued
Array ( [id] => 7571030 [patent_doc_number] => 20110266686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/020235 [patent_app_country] => US [patent_app_date] => 2011-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4560 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20110266686.pdf [firstpage_image] =>[orig_patent_app_number] => 13020235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/020235
Semiconductor device and method of manufacturing the same Feb 2, 2011 Issued
Array ( [id] => 6161410 [patent_doc_number] => 20110193224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/020126 [patent_app_country] => US [patent_app_date] => 2011-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3289 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20110193224.pdf [firstpage_image] =>[orig_patent_app_number] => 13020126 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/020126
SEMICONDUCTOR DEVICE Feb 2, 2011 Abandoned
Array ( [id] => 6185375 [patent_doc_number] => 20110124158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'THERMAL ENHANCED UPPER AND DUAL HEAT SINK EXPOSED MOLDED LEADLESS PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/019488 [patent_app_country] => US [patent_app_date] => 2011-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3615 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20110124158.pdf [firstpage_image] =>[orig_patent_app_number] => 13019488 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/019488
Thermal enhanced upper and dual heat sink exposed molded leadless package and method Feb 1, 2011 Issued
Array ( [id] => 9876042 [patent_doc_number] => 08963315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Semiconductor device with surface electrodes' [patent_app_type] => utility [patent_app_number] => 13/019390 [patent_app_country] => US [patent_app_date] => 2011-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 68 [patent_no_of_words] => 17903 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13019390 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/019390
Semiconductor device with surface electrodes Feb 1, 2011 Issued
Array ( [id] => 8321400 [patent_doc_number] => 20120193809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/018790 [patent_app_country] => US [patent_app_date] => 2011-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13018790 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/018790
INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME Jan 31, 2011 Abandoned
Array ( [id] => 8321402 [patent_doc_number] => 20120193808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'BONDED STACKED WAFERS AND METHODS OF ELECTROPLATING BONDED STACKED WAFERS' [patent_app_type] => utility [patent_app_number] => 13/018534 [patent_app_country] => US [patent_app_date] => 2011-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13018534 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/018534
Bonded stacked wafers and methods of electroplating bonded stacked wafers Jan 31, 2011 Issued
Array ( [id] => 7666876 [patent_doc_number] => 20110316145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'NANO/MICRO-STRUCTURE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/018444 [patent_app_country] => US [patent_app_date] => 2011-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2506 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13018444 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/018444
NANO/MICRO-STRUCTURE AND FABRICATION METHOD THEREOF Jan 31, 2011 Abandoned
Array ( [id] => 6161409 [patent_doc_number] => 20110193223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SEMICONDUCTOR DEVICE, CHIP-ON-CHIP MOUNTING STRUCTURE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND METHOD OF FORMING THE CHIP-ON-CHIP MOUNTING STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/018723 [patent_app_country] => US [patent_app_date] => 2011-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4593 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20110193223.pdf [firstpage_image] =>[orig_patent_app_number] => 13018723 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/018723
SEMICONDUCTOR DEVICE, CHIP-ON-CHIP MOUNTING STRUCTURE, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND METHOD OF FORMING THE CHIP-ON-CHIP MOUNTING STRUCTURE Jan 31, 2011 Abandoned
Array ( [id] => 10870239 [patent_doc_number] => 08895435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Polysilicon layer and method of forming the same' [patent_app_type] => utility [patent_app_number] => 13/018009 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3853 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13018009 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/018009
Polysilicon layer and method of forming the same Jan 30, 2011 Issued
Array ( [id] => 8321381 [patent_doc_number] => 20120193795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING AN AIRBRIDGE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/017414 [patent_app_country] => US [patent_app_date] => 2011-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4340 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13017414 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/017414
Semiconductor device having an airbridge and method of fabricating the same Jan 30, 2011 Issued
Array ( [id] => 6161367 [patent_doc_number] => 20110193204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/016611 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20110193204.pdf [firstpage_image] =>[orig_patent_app_number] => 13016611 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/016611
SEMICONDUCTOR DEVICE Jan 27, 2011 Abandoned
Array ( [id] => 6057671 [patent_doc_number] => 20110113391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'LAYOUT DESIGN TOOL' [patent_app_type] => utility [patent_app_number] => 13/006659 [patent_app_country] => US [patent_app_date] => 2011-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4441 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113391.pdf [firstpage_image] =>[orig_patent_app_number] => 13006659 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/006659
Layout design tool for semiconductor integrated circuit Jan 13, 2011 Issued
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